On 05/15/2014 12:22 PM, Keir Fraser wrote:
>>
>> Are we chasing hardware errata here? Or did someone go off and *assume*
>> that the x86 hardware architecture work a certain way? Or is there
>> something way more subtle going on?
>
> See Intel Developer's Manual Vol 3 Section 4.10.4.3, 3rd bullet... This
> is expected behaviour, probably to make copy-on-write faults faster.
>
Hm, yes. My memory of this comes from before these formal rules were
written down... I guess there is some wiggle room in there, presumably
as you say, for performance reasons (or implementation leeway, which is
another way to say performance.)
This does make a P bit switch architecturally different from W or NX, so
I'm okay with that, but I would like the patch adjusted in the following
ways:
1. Put in an explicit comment about the architectural difference
between the P bit on one hand and an W and NX on the other; an SDM
reference is good, and *why* this makes the specific filtering
correct.
2. Please use the standard format for multiline comments;
/*
* blah
* blah
*/
With that this should be okay.
-hpa
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