>-----Original Message-----
>From: Peter Zijlstra [mailto:pet...@infradead.org]
>Sent: Thursday, March 06, 2014 5:07 PM
>To: Tony Lu
>Cc: Paul Mackerras; Ingo Molnar; Arnaldo Carvalho de Melo; Chris Metcalf;
>linux-kernel@vger.kernel.org
>Subject: Re: [PATCH 3/4] tile/perf: Support perf_events on tilegx and tilepro
>
>On Thu, Mar 06, 2014 at 06:26:11AM +0000, Tony Lu wrote:
>> +static const int tile_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
>> + [PERF_COUNT_HW_CACHE_OP_MAX]
>> + [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
>> +[C(L1D)] = {
>> + [C(OP_READ)] = {
>> + [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
>> + [C(RESULT_MISS)] = 0x21, /* RD_MISS */
>> + },
>> + [C(OP_WRITE)] = {
>> + [C(RESULT_ACCESS)] = 0x22, /* WR_MISS */
>> + [C(RESULT_MISS)] = TILE_OP_UNSUPP,
>> + },
>
>If that's the wr_miss event as the comment says, it should probably be
>listed one down.
Yes, you are right. Thanks for pointing it out. It should be:
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+ [C(RESULT_MISS)] = 0x22, /* WR_MISS */
+ },
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