Hi, Follow the mailing-list http://comments.gmane.org/gmane.linux.ports.arm.omap/31686
>>Setting the L1 cache line size larger than it actually is should be safe. the written code expected as L1_CACHE_BYTES should be real cache line size has bug. It looks like that flush_pfn_alias function should be fixed. Anybody to have another opinion? Cheers, JS -----Original Message----- From: 이정승 [mailto:js07....@samsung.com] Sent: Tuesday, January 14, 2014 10:43 PM To: 'catalin.mari...@arm.com'; 'linux-arm-ker...@lists.infradead.org' Cc: 'li...@arm.linux.org.uk' Subject: Question on flush_pfn_alias function. Dear Catalin, I found below function and that clean and invalidate data cache range with "mcrr" The end address is end of page - L1_CACHE_BYTES (e.g. 32 , 64) +static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) { + unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << +PAGE_SHIFT); + + set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); + flush_tlb_kernel_page(to); + + asm( "mcrr p15, 0, %1, %0, c14\n" + " mcrr p15, 0, %1, %0, c5\n" + : + : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES) + : "cc"); +} However, follow the mail and current setting in vanilla kernel, L1_CACHE_BYTES of Cortex A9 will be 64 not 32. http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/183316.html I think that could be problem. What is your opinion? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
