Sirs,
I think that I confirmed the bug that I have post some days ago.
Checking the specs updates from Intel I have found this report:
===========
L30. Changes to CR3 Register Do Not Fence Pending Instruction Page Walks
Problem: When software writes to the CR3 register, it is expected that
all previous/outstanding code, data accesses and page walks are
completed using the previous value in CR3 register. Due to this
erratum, it is possible that a pending instruction page walk is still
in progress, resulting in an access (to the PDE portion of the page
table) that may be directed to an incorrect memory address.
Implication: The results of the access to the PDE will not be consumed
by the processor so the return of incorrect data is benign. However,
the system may hang if the access to the PDE does not complete with
data (e.g. infinite number of retries).
Workaround: There is no workaround.
===========
And the code of reboot ( that follows ) uses the CR3 register to go
from protected mode to real mode. My Processor SSpec is SL7C4 and
processor signature 0F33h. Can someone from Intel confirm this and if
possible point to any newer workaround?
Thanks
Camilo
version 2.4.28
arch/i386/kernel/process.c Line 248
static unsigned char real_mode_switch [] =
{
0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax
*/
0x66, 0x83, 0xe0, 0x11, /* andl
$0x00000011,%eax */
0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl
$0x60000000,%eax */
0x66, 0x0f, 0x22, 0xc0, /* movl %eax,%cr0
*/
===> 0x66, 0x0f, 0x22, 0xd8, /* movl %eax,%cr3
*/
0x66, 0x0f, 0x20, 0xc3, /* movl %cr0,%ebx
*/
0x66, 0x81, 0xe3, 0x00, 0x00, 0x00, 0x60, /* andl
$0x60000000,%ebx */
0x74, 0x02, /* jz f
*/
0x0f, 0x09, /* wbinvd
*/
0x24, 0x10, /* f: andb $0x10,al
*/
0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0
*/
}
version
arch/i386/kernel/reboot.c Line 192
static unsigned char real_mode_switch [] =
{
0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax
*/
0x66, 0x83, 0xe0, 0x11, /* andl
$0x00000011,%eax */
0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl
$0x60000000,%eax */
0x66, 0x0f, 0x22, 0xc0, /* movl %eax,%cr0
*/
===> 0x66, 0x0f, 0x22, 0xd8, /* movl %eax,%cr3
*/
0x66, 0x0f, 0x20, 0xc3, /* movl %cr0,%ebx
*/
0x66, 0x81, 0xe3, 0x00, 0x00, 0x00, 0x60, /* andl
$0x60000000,%ebx */
0x74, 0x02, /* jz f
*/
0x0f, 0x09, /* wbinvd
*/
0x24, 0x10, /* f: andb $0x10,al
*/
0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0
*/
}
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