This patch is originally from Jake Moilanen <[EMAIL PROTECTED]>,
substantially modified by me.
On PPC64 systems with a hypervisor, we can't set the Data Address
Breakpoint Register (DABR) directly, we have to do it through a
hypervisor call.
Signed-off-by: Jake Moilanen <[EMAIL PROTECTED]>
Signed-off-by: Paul Mackerras <[EMAIL PROTECTED]>
diff -urN linux-2.5/arch/ppc64/xmon/xmon.c test/arch/ppc64/xmon/xmon.c
--- linux-2.5/arch/ppc64/xmon/xmon.c 2005-01-12 18:20:48.000000000 +1100
+++ test/arch/ppc64/xmon/xmon.c 2005-01-22 10:55:46.664345064 +1100
@@ -624,6 +624,17 @@
return 0;
}
+/* On systems with a hypervisor, we can't set the DABR
+ (data address breakpoint register) directly. */
+static void set_controlled_dabr(unsigned long val)
+{
+ if (systemcfg->platform == PLATFORM_PSERIES_LPAR) {
+ int rc = plpar_hcall_norets(H_SET_DABR, val);
+ if (rc != H_Success)
+ xmon_printf("Warning: setting DABR failed (%d)\n", rc);
+ } else
+ set_dabr(val);
+}
static struct bpt *at_breakpoint(unsigned long pc)
{
@@ -711,7 +722,7 @@
static void insert_cpu_bpts(void)
{
if (dabr.enabled)
- set_dabr(dabr.address | (dabr.enabled & 7));
+ set_controlled_dabr(dabr.address | (dabr.enabled & 7));
if (iabr && (cur_cpu_spec->cpu_features & CPU_FTR_IABR))
set_iabr(iabr->address
| (iabr->enabled & (BP_IABR|BP_IABR_TE)));
@@ -739,7 +750,7 @@
static void remove_cpu_bpts(void)
{
- set_dabr(0);
+ set_controlled_dabr(0);
if ((cur_cpu_spec->cpu_features & CPU_FTR_IABR))
set_iabr(0);
}
@@ -1049,8 +1060,8 @@
"b <addr> [cnt] set breakpoint at given instr addr\n"
"bc clear all breakpoints\n"
"bc <n/addr> clear breakpoint number n or at addr\n"
- "bi <addr> [cnt] set hardware instr breakpoint (broken?)\n"
- "bd <addr> [cnt] set hardware data breakpoint (broken?)\n"
+ "bi <addr> [cnt] set hardware instr breakpoint (POWER3/RS64 only)\n"
+ "bd <addr> [cnt] set hardware data breakpoint\n"
"";
static void
-
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