On 10/07/2013 04:55 PM, H. Peter Anvin wrote: > If I recall correctly we simply poked at the FPGA directly from userspace. Not ideal by any means and also meant we had to have a backup recovery mechanism as it meant that the FPGA had to be programmed already as the bus interface was in soft IP.
ok. How was that physical hardware connection to device you wanted to talk? Was it any special IP with MMIO? Or gpio jtag emulation or similar? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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