cmpxchg64_relaxed can be used to provide barrier-less semantics for a 64-bit cmpxchg operation in cases where the strong memory ordering is not required. A useful use-case for this is in the recently merged lockless lockref code.
This patch implements a dummy implementation for ia64, which could probably be improved by removing the half barrier associated with the default cmpxchg64 macro. Cc: Tony Luck <tony.l...@intel.com> Signed-off-by: Will Deacon <will.dea...@arm.com> --- arch/ia64/include/uapi/asm/cmpxchg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/ia64/include/uapi/asm/cmpxchg.h b/arch/ia64/include/uapi/asm/cmpxchg.h index 4f37dbb..8984b6e 100644 --- a/arch/ia64/include/uapi/asm/cmpxchg.h +++ b/arch/ia64/include/uapi/asm/cmpxchg.h @@ -124,6 +124,7 @@ extern long ia64_cmpxchg_called_with_bad_pointer(void); #define cmpxchg_local cmpxchg #define cmpxchg64_local cmpxchg64 +#define cmpxchg64_relaxed cmpxchg64 #ifdef CONFIG_IA64_DEBUG_CMPXCHG # define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; -- 1.8.2.2 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
