On 09/19/13 13:00, Quentin Armitage wrote:
There appears to be an error in the second address of the second XOR
engine in the Kirkwood SoC device tree, which is specified as 0xd0b00
but should be 0x60b00.
For confirmation of address see
http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
table 581 page 658.
Also see definition of XOR1_HIGH_PHYS_BASE in
arch/arm/mach-kirkwood/include/mach/kirkwood.h
#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
Signed-off-by: Quentin Armitage <quen...@armitage.org.uk>
I double-checked the references, typo and fix are correct.
Reviewed-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com>
---
arch/arm/boot/dts/kirkwood.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/kirkwood.dtsi
b/arch/arm/boot/dts/kirkwood.dtsi
index cf7aeaf..63d4066 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -167,7 +167,7 @@
xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
- 0xd0B00 0x100>;
+ 0x60B00 0x100>;
status = "okay";
clocks = <&gate_clk 16>;
---
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