From: Andi Kleen <a...@linux.intel.com>
[The patch to enable this in the user tools has been sent separately]
With the earlier patches to automatically try cpu// and add
a precise sys attribute, we can now enable PEBS for the mem-loads,
mem-stores events everywhere.
This allows to use
perf record -e mem-loads ...
instead of
perf record -e cpu/mem-loads/p ...
Always use precise=2 even though it is costly pre-Haswell
Cc: eran...@google.com
v2: Different white space
v3: Always use precise=2, as people seem to think overhead doesn't matter.
Signed-off-by: Andi Kleen <a...@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
b/arch/x86/kernel/cpu/perf_event_intel.c
index fbc9210..ef9236b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -176,9 +176,12 @@ static struct extra_reg intel_snbep_extra_regs[]
__read_mostly = {
EVENT_EXTRA_END
};
-EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
-EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
-EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
+EVENT_ATTR_STR(mem-loads, mem_ld_nhm,
+ "event=0x0b,umask=0x10,ldlat=3,precise=2");
+EVENT_ATTR_STR(mem-loads, mem_ld_snb,
+ "event=0xcd,umask=0x1,ldlat=3,precise=2");
+EVENT_ATTR_STR(mem-stores, mem_st_snb,
+ "event=0xcd,umask=0x2,precise=2");
struct attribute *nhm_events_attrs[] = {
EVENT_PTR(mem_ld_nhm),
@@ -2034,8 +2037,9 @@ static __init void intel_nehalem_quirk(void)
}
}
-EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
-EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
+EVENT_ATTR_STR(mem-loads, mem_ld_hsw,
+ "event=0xcd,umask=0x1,ldlat=3,precise=2");
+EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82,precise=2")
static struct attribute *hsw_events_attrs[] = {
EVENT_PTR(mem_ld_hsw),
--
1.8.1.4
--
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