On Monday, July 08, 2013 2:06 PM, Jingoo Han wrote: > On Friday, July 05, 2013 7:44 PM, Pratyush Anand wrote: > > On 7/5/2013 1:59 PM, Jingoo Han wrote: > > > Exynos PCIe IP consists of Synopsys specific part and Exynos > > > specific part. Only core block is a Synopsys designware part; > > > other parts are Exynos specific. > > > Also, the Synopsys designware part can be shared with other > > > platforms; thus, it can be split two parts such as Synopsys > > > designware part and Exynos specific part. > > > > > > > A quick and nice job :) > > Just few minor comments. > > Thank you. > Without your comment, it could be done. :)
Oops, it is a typo. Without your comment, it could 'NOT' be done. :) Thank you for your comment. It is very helpful. Best regards, Jingoo Han -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
