On Tue, 2013-06-25 at 18:53 -0700, Darren Hart wrote: > The MinnowBoard uses an AR803x PHY with the PCH GBE. > > It does not implement the RGMII 2ns TX clock delay in the trace routing > nor via strapping. Add a detection method for the board and the PHY and > enable the tx clock delay via the registers. > > This PHY will hibernate without link for 10 seconds. Ensure the PHY is > awake for probe and then disable hibernation. A future improvement would > be to convert pch_gbe to using PHYLIB and making sure we can wake the > PHY at the necessary times rather than permanently disabling it. > > Use the MinnowBoard PCI subsystem ID to identify the board and setup the > appropriate callbacks in a new pci_id driver_data structure. >
Per the discussion on the minnowboard platform drivers in this series (which provide the minnow_phy_reset() function), I will be rewriting this patch to provide its own phy_physical_reset() or similar which will look like the other two phy functions I've added and will take a GPIO line as an argument, determined by pci_id. Please disregard this patch for now. Thanks, -- Darren Hart Intel Open Source Technology Center Yocto Project - Technical Lead - Linux Kernel -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
