On 17.05.13 11:45:51, Borislav Petkov wrote: > On Fri, May 17, 2013 at 11:27:41AM +0200, Peter Zijlstra wrote: > > But not all x86 hardware even has the stuff enumerated in CPUID, and > > afaict Intel and AMD use a different CPUID bit as well, so what's > > init_hw_perf_events() to do? > > Yeah, I think the best solution would be if we force-enable the CPUID > bit on F10h very early and teach amd_pmu_init() to look at it. I even > had a patch which does something like that. I could dust it off and give > it a try... I just hope we can actually enable a reserved bit in CPUID.
The cpuid bit indicates perfctrs that do not exist, this will setup a wrong msr range on f10h. I guess the warning is harmless and the code works properly, but I can't tell for sure now and need to look at it. Also, the problem occurs on f15h there *no* core perfctrs exist but are expected, not on a f10h system. -Robert -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
