On Thu, May 09, 2013 at 11:16:07AM +0200, Paolo Bonzini wrote:
> This is an almost-undocumented instruction available in 32-bit mode.
> I say "almost" undocumented because AMD documents it in their opcode
> maps just to say that it is unavailable in 64-bit mode (sections
> "A.2.1 One-Byte Opcodes" and "B.3 Invalid and Reassigned Instructions
> in 64-Bit Mode").
>
> It is roughly equivalent to "sbb %al, %al" except it does not
> set the flags. Use fastop to emulate it, but do not use the opcode
> directly because it would fail if the host is 64-bit!
>
> Reported-by: Jun'ichi Nomura <j-nom...@ce.jp.nec.com>
> Cc: sta...@kernel.org # 3.9
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
> ---
> arch/x86/kvm/emulate.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
> index 210bb4e..f62d4c8 100644
> --- a/arch/x86/kvm/emulate.c
> +++ b/arch/x86/kvm/emulate.c
> @@ -534,6 +534,9 @@ FOP_SETCC(setle)
> FOP_SETCC(setnle)
> FOP_END;
>
> +FOP_START(salc) "pushf; sbb %al, %al; popf; ret \n\t"
FOP_RET
> +FOP_END;
> +
> #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex)
> \
> do { \
> unsigned long _tmp; \
> @@ -3951,7 +3954,8 @@ static const struct opcode opcode_table[256] = {
> G(Src2One | ByteOp, group2), G(Src2One, group2),
> G(Src2CL | ByteOp, group2), G(Src2CL, group2),
> I(DstAcc | SrcImmUByte | No64, em_aam),
> - I(DstAcc | SrcImmUByte | No64, em_aad), N,
> + I(DstAcc | SrcImmUByte | No64, em_aad),
> + F(DstAcc | ByteOp | No64, em_salc),
> I(DstAcc | SrcXLat | ByteOp, em_mov),
> /* 0xD8 - 0xDF */
> N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
> --
> 1.8.1.4
--
Gleb.
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