On Mon, May 06, 2013 at 10:12:38PM +0100, Will Deacon wrote: > The other (hopefully also wrong) worry that I had was when the manual > states that: > > `If the virtual and physical addresses for a LDx_L and STx_C sequence are > not within the same naturally aligned 16-byte sections of virtual and > physical memory, that sequence may always fail, or may succeed despite > another processor’s store to the lock range; hence, no useful program > should do this' > > This seems like it might have a curious interaction with CoW paging if > userspace is trying to use these instructions for a lock, since the > physical address for the conditional store might differ from the one which > was passed to the load due to CoW triggered by a different thread. Anyway, > I was still thinking about that one and haven't got as far as TLB > invalidation yet :)
In case anybody is interested, the software broadcasting of TLB maintenance solves this problem because the PAL_rti on the ret_to_user path will clear the lock flag. Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
