On Sat, Feb 16, 2013 at 06:03:51PM +0100, Daniel Mack wrote: > The register layout is described on page 26, and they call their > registers 'subaddresses'. Up to sub-address 0x1c, I see no problem > mapping that to a simple 8-bit regmap layout, but above that, access > gets trickier because registers change their sizes, which breaks the cache.
The regmap I/O code isn't making any effort to support such devices, the hardware is just too crazy to worry about. The best you can do is use the no-bus support and open code your physical I/O so you can still use the cache.
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