Would you like to take it? It is needed by Linux OSVs.
Thanks
-Youquan
On Tue, Dec 18, 2012 at 12:20:23PM -0500, Youquan Song wrote:
> Run in perf utility at Ivybridge EP server, encouter "not supported" event
>
> <not supported> L1-dcache-loads
> <not supported> L1-dcache-load-misses
> <not supported> L1-dcache-stores
> <not supported> L1-dcache-store-misses
> <not supported> L1-dcache-prefetches
> <not supported> L1-dcache-prefetch-misses
>
> This patch add the support for this processor.
>
> Reviewed-by: Andi Kleen <a...@linux.intel.com>
> Signed-off-by: Youquan Song <youquan.s...@intel.com>
> ---
> arch/x86/kernel/cpu/perf_event_intel.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
> b/arch/x86/kernel/cpu/perf_event_intel.c
> index 324bb52..aea3503 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2075,6 +2075,7 @@ __init int intel_pmu_init(void)
> pr_cont("SandyBridge events, ");
> break;
> case 58: /* IvyBridge */
> + case 62: /* IvyBridge EP */
> memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
> sizeof(hw_cache_event_ids));
> memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
> --
> 1.6.4.2
>
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