On Sat, Dec 15, 2012 at 2:17 PM, H. Peter Anvin <h...@zytor.com> wrote: > On 12/15/2012 02:13 PM, Yinghai Lu wrote: >> >> >> AMD system could have all mem between TOLM and TOHM all WB, and don >> need to set them in MTRRs entries. >> > > I include the TOM2 mechanism in the overall umbrella of MTRRs for this > purpose. > > >> and also your switchover change that handle cross 1G, and 512g, and it >> is not 1G aligned. >> for example, if kernel at 4095G+512M, it will map from 4095G+512M to >> 4096G + 512M. > > > That is for the kernel region itself (that code is actually unchanged from > the current code), and yes, we could cap that one to _end if there are > systems which have bugs in that area. The dynamic page tables map 1G > aligned at a time.
dynamic should be 2M too. AMD system: http://git.kernel.org/?p=linux/kernel/git/tip/tip.git;a=commitdiff;h=66520ebc2df3fe52eb4792f8101fac573b766baf BIOS-e820: [mem 0x0000000100000000-0x000000e037ffffff] usable BIOS-e820: [mem 0x000000e038000000-0x000000fcffffffff] reserved BIOS-e820: [mem 0x0000010000000000-0x0000011ffeffffff] usable the hole is not 1G aligned. or HT region is from e040000000 ? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
