On Fri, 2012-12-07 at 19:02 +0000, Will Deacon wrote: > For ARMv7, there are small subsets of instructions for ARM and Thumb which > are guaranteed to be atomic wrt concurrent modification and execution of > the instruction stream between different processors: > > Thumb: The 16-bit encodings of the B, NOP, BKPT, and SVC instructions. > ARM: The B, BL, NOP, BKPT, SVC, HVC, and SMC instructions. > > but before your eyes light up at the presence of the BKPT instruction in > that list; we don't actually use that in Linux and instead leave it for > external (i.e. JTAG) debuggers so that they can operate without getting > tangled up with spurious traps from the OS. Linux actually picks its own > undefined instructions, which are obviously not included in the lists above.
My eyes actually lit up with the B instruction :-) As Jon showed, we could use a 16bit jump instead. Add the B to jump over the other half of the call (to all places that you want to modify). Send a sync to all CPUs to flush their caches. Modify the other half of the call, send another sync, and then modify the first half. > > Also note that the 16-bit limitation for Thumb instructions above can > actually be used to modify *half* of a BL instruction but, to keep things > exciting, the PC-relative immediate is split across the two halves. However, > you could in theory mess around with bottom 10 bits or so, depending on the > exact encoding... > > Obviously this doesn't preclude the need for cache maintenance on both D and > I side, but the atomicity guarantees are as I've described above. Right. Thanks for the update. -- Steve -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
