On Wed, Nov 28, 2012 at 11:50:30AM -0800, H. Peter Anvin wrote:
> From: "H. Peter Anvin" <h...@linux.intel.com>
>
> Simplify the implementation of sync_core() for the case where we may
> not have the CPUID instruction available.
>
> Signed-off-by: H. Peter Anvin <h...@linux.intel.com>
> ---
> arch/x86/include/asm/processor.h | 27 +++++++++++++++++----------
> 1 file changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/arch/x86/include/asm/processor.h
> b/arch/x86/include/asm/processor.h
> index 9a4ee46..b381df7 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -673,17 +673,24 @@ static inline void sync_core(void)
> int tmp;
>
> #ifdef CONFIG_M486
> - if (boot_cpu_data.x86 < 5)
> - /* There is no speculative execution.
> - * jmp is a barrier to prefetching. */
> - asm volatile("jmp 1f\n1:\n" ::: "memory");
> - else
> + /*
> + * Do a CPUID if available, otherwise do a jump. The jump
> + * can conveniently enough be the jump around CPUID.
> + */
> + asm volatile("cmpl %2,%1\n\t"
> + "jl 1f\n\t"
> + "cpuid\n"
> + "1:"
> + : "=a" (tmp)
> + : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
> + : "ebx", "ecx", "edx", "memory");
> +#else
> + /* cpuid is a barrier to speculative execution.
> + * Prefetched instructions are automatically
> + * invalidated when modified. */
While at it, you could correct this comment to adhere to kernel coding
style:
/*
* cpuid is a barrier...
* ...
*/
> + asm volatile("cpuid" : "=a" (tmp) : "0" (1)
> + : "ebx", "ecx", "edx", "memory");
... and then write this in its shorter form:
tmp = cpuid_eax(1);
to have it a bit easier on the eyes.
Thanks.
--
Regards/Gruss,
Boris.
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