On 11/26/2012 09:56 PM, Dan Williams wrote: > On Fri, Nov 16, 2012 at 3:26 PM, Dave Jiang <dave.ji...@intel.com> wrote: >> The CHANERRMSK_INT register should be 0. The existing code set a value >> for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that >> has been fixed when the hardware was released. There is no need for this >> code. >> >> Signed-off-by: Dave Jiang <dave.ji...@intel.com> >> --- >> >> drivers/dma/ioat/dma_v3.c | 8 ++------ >> 1 file changed, 2 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c >> index f7f1dc6..60c15c4 100644 >> --- a/drivers/dma/ioat/dma_v3.c >> +++ b/drivers/dma/ioat/dma_v3.c >> @@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common >> *chan) >> chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); >> writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); >> >> - /* -= IOAT ver.3 workarounds =- */ >> - /* Write CHANERRMSK_INT with 3E07h to mask out the errors >> - * that can cause stability issues for IOAT ver.3, and clear any >> - * pending errors >> - */ >> - pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, >> 0x3e07); >> + /* clearn CHANERRMASK_INT and clear any pending errors */ >> + pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0); > Can we get rid of this write / register access altogether? Then the > driver will load on systems where extended pci configuration space is > not available.
So this entire thing does read and write to a mask register and the error register. Were you wanting both removed? I think we may still want to clear the error register. If that's the case, it doesn't get around the extended PCI config space issue. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
