On Mon, Oct 29, 2012 at 10:06:15AM -0700, Linus Torvalds wrote: > On Mon, Oct 29, 2012 at 9:57 AM, Borislav Petkov <b...@alien8.de> wrote: > > > > On current AMD64 processors, > > Can you verify that this is true for older cpu's too (ie the old > pre-64-bit ones, say K6 and original Athlon)?
Albeit with a slight delay, the answer is yes: all AMD cpus automatically invalidate cached TLB entries (and intermediate walk results, for that matter) on a #PF. I don't know, however, whether it would be prudent to have some sort of a cheap assertion in the code (cheaper than INVLPG %ADDR, although on older cpus we do MOV CR3) just in case. This should be enabled only with DEBUG_VM on, of course... HTH. -- Regards/Gruss, Boris. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
