On Fri, Nov 09, 2012 at 10:50:25PM +1100, Neil Brown wrote: > On Fri, 09 Nov 2012 12:39:05 +0100 "H. Peter Anvin" <h...@zytor.com> wrote: > > > Sorry, we cannot share those at this time since the hardwarenis not yet > > released. > > Can I take that to imply "Acked-by: "H. Peter Anvin" <h...@zytor.com>" ?? > > It would be nice to have at least a statement like: > These patches have been tested both with the user-space testing tool and in > a RAID6 md array and the pass all test. While we cannot release performance > numbers as the hardwere is not released, we can confirm that on that hardware > the performance with these patches is faster than without. > > I guess I should be able to assume that - surely the patches would not be > posted if it were not true... But I like to avoid assuming when I can.
Hi Neil, That assumption is correct. The patch was tested and benchmarked before submission. You'll notice that this code is very similar to the SSSE3-optimized recovery routines I wrote earlier. This implementation extends that same algorithm from 128-bit registers to 256-bit registers. Thanks. -- Jim Kukunas Intel Open Source Technology Center
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