Re: Q: explicit alignment control for the slab allocator

[Jes Sorensen]

>>>>> "Manfred" == Manfred Spraul <[EMAIL PROTECTED]> writes:

Manfred> Mark Hemment wrote:
>> As no one uses the feature it could well be broken, but is that a
>> reason to change its meaning?

Manfred> Some hardware drivers use HW_CACHEALIGN and assume certain
Manfred> byte alignments, and arm needs 1024 byte aligned blocks.

Isn't that just a reinvention of SMP_CACHE_BYTES? Or are there
actually machines out there where the inbetween CPU cache line size
differs from the between CPU and DMA controller cache line size?

Jes
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