Jeff Garzik writes:
 > And in another message, On Mon, 12 Feb 2001, David S. Miller wrote:
 > > 3) The acenic/gbit performance anomalies have been cured
 > >    by reverting the PCI mem_inval tweaks.
 > 
 > 
 > Just to be clear, acenic should or should not use MWI?
 > 
 > And can a general rule be applied here?  Newer Tulip hardware also
 > has the ability to enable/disable MWI usage, IIRC.

I think this is an Acenic specific issue.  The second processor on the
Acenic board is only there to work around bugs in their DMA
controller.

Later,
David S. Miller
[EMAIL PROTECTED]
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