> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
> b/arch/x86/kernel/cpu/perf_event_intel.c
> index 7f2739e..0d3d63a 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
> break;
>
> case 28: /* Atom */
> + case 54: /* Cedariew */
Ack. We currently miss some more 32nm Atoms too, will send patches soon.
> memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
> sizeof(hw_cache_event_ids));
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> index 520b426..da02e9c 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> @@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
> * to have an operational LBR which can freeze
> * on PMU interrupt
> */
> - if (boot_cpu_data.x86_mask < 10) {
> + if (boot_cpu_data.x86_model == 28
> + && boot_cpu_data.x86_mask < 10) {
Is that correct?
-Andi
--
[email protected] -- Speaking for myself only.
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