On Tue, Jul 24, 2012 at 8:50 AM, John Crispin <blo...@openwrt.org> wrote:
> Implement support for pinctrl on lantiq/xway socs. The IO core found on these > socs has the registers for pinctrl, pinconf and gpio mixed up in the same > register range. As the gpio_chip handling is only a few lines, the driver also > implements the gpio functionality. This obseletes the old gpio driver that was > located in the arch/ folder. > > Signed-off-by: John Crispin <blo...@openwrt.org> > Acked-by: Linus Walleij <linus.wall...@linaro.org> I still ACK it, just a comment: > +/* these are the offsets to our registers */ > +#define GPIO_BASE(p) (REG_OFF * PORT(p)) > +#define GPIO_OUT(p) GPIO_BASE(p) > +#define GPIO_IN(p) (GPIO_BASE(p) + 0x04) > +#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08) > +#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C) > +#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10) > +#define GPIO_OD(p) (GPIO_BASE(p) + 0x14) > +#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) > +#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) > + > +/* the 1/2 port needs special offsets for some registers */ > +#define GPIO3_OD (GPIO_BASE(0) + 0x24) > +#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) > +#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) > +#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24) > + > +/* macros to help us access the registers */ > +#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p))) > +#define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r) > +#define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r) These are a bit confusing since much of this stuff is not dealing with GPIO at all (but some pulling, open draining etc). Consider renaming some of these some day. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
