On Fri, Feb 15, 2008 at 5:02 AM, Alan Cox <[EMAIL PROTECTED]> wrote: > > Is there any way to get PIO to burst over the PCI bus in the read and > > write direction? My device has 4 BAR registers, but the area where I > > I think you are doign about as well as the X folks did when they spent > time on trying to optimise pio transfers to and from graphics card RAM. >
That's good to know. Do you have a link or anything to their discussion or some key words that I could hunt it down? > > > Any ideas would be really appreciated, > > Put a DMA controller on it ;) Ugh.. sadly that's what's coming. I really don't get why the northbridge cannot burst however. If the memory is mapped prefetchable and you have to do a PCI read through 3 PCIe bridges to finally get to your device it seems like it would _really_ behoove the bridge to do a Memory read multiple and get the whole cache line. I have searched around a lot and there doesn't seem to be any info at all on how you can persuade these bridges to do different PCI commands or burst. I don't know why.... thanks again for your help, dan -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
