On Fri, Sep 18, 2026 at 1:56 AM Tina Zhang <[email protected]> wrote: > > When the x86 emulator encounters an instruction intercepted by L1, > svm_check_intercept() synthesizes a nested VM-Exit without fresh hardware > DecodeAssist state. Populate the architectural EXITINFO1 field when > DecodeAssists is exposed to L1. > > Provide the GPR number for MOV CR/DR, the interrupt vector for INTn, and > the linear address for INVLPG. Preserve the MOV-to-CR0 decode information > when a selective CR0 write intercept is triggered. Leave EXITINFO1 clear > for CLTS, LMSW, SMSW, and INVLPGA; the INVLPGA address remains in guest > rAX. Leave EXITINFO1 unchanged when DecodeAssists is not exposed, and > leave unrelated intercepts unchanged. > > Signed-off-by: Tina Zhang <[email protected]>
I think Sashiko is hallucinating. Reviewed-by: Jim Mattson <[email protected]>
