On 8/13/26 2:36 AM, [email protected] wrote: > From: Manish Honap <[email protected]> > > The CXL component and HDM decoder register layout is spec-defined and is > needed by consumers outside the CXL subsystem such as vfio-cxl, which > cannot include the private drivers/cxl/cxl.h. Move those defines to a new > uapi header, the way PCI register offsets live in uapi pci_regs.h, and > include it from drivers/cxl/cxl.h so existing users are unchanged. Wouldn't the proper location be include/cxl/cxl.h instead if it's only being shared by vfio-cxl kernel component? Unless there are expectation of user side usage for those definitions? If so then should say so here. DJ > > No functional change; the GENMASK and BIT forms are written as plain > values as an uAPI header requirement. > > Signed-off-by: Manish Honap <[email protected]> > --- > MAINTAINERS | 1 + > drivers/cxl/cxl.h | 47 +----------------------------- > include/uapi/cxl/cxl_regs.h | 58 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 60 insertions(+), 46 deletions(-) > create mode 100644 include/uapi/cxl/cxl_regs.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 5114e6db7307..c665bf8f1a28 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -6528,6 +6528,7 @@ F: Documentation/driver-api/cxl > F: Documentation/userspace-api/fwctl/fwctl-cxl.rst > F: drivers/cxl/ > F: include/cxl/ > +F: include/uapi/cxl/ > F: include/uapi/linux/cxl_mem.h > F: tools/testing/cxl/ > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index c795cce0fcbc..2893b2427be1 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -13,6 +13,7 @@ > #include <linux/io.h> > #include <linux/range.h> > #include <cxl/cxl.h> > +#include <cxl/cxl_regs.h> > > extern const struct nvdimm_security_ops *cxl_security_ops; > > @@ -24,52 +25,6 @@ extern const struct nvdimm_security_ops *cxl_security_ops; > * (port-driver, region-driver, nvdimm object-drivers... etc). > */ > > -/* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ > -#define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K > - > -/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ > -#define CXL_CM_OFFSET 0x1000 > -#define CXL_CM_CAP_HDR_OFFSET 0x0 > -#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) > -#define CM_CAP_HDR_CAP_ID 1 > -#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) > -#define CM_CAP_HDR_CAP_VERSION 1 > -#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) > -#define CM_CAP_HDR_CACHE_MEM_VERSION 1 > -#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) > -#define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) > - > -#define CXL_CM_CAP_CAP_ID_RAS 0x2 > -#define CXL_CM_CAP_CAP_ID_HDM 0x5 > -#define CXL_CM_CAP_CAP_HDM_VERSION 1 > - > -/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ > -#define CXL_HDM_DECODER_CAP_OFFSET 0x0 > -#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) > -#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) > -#define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) > -#define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) > -#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) > -#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) > -#define CXL_HDM_DECODER_CTRL_OFFSET 0x4 > -#define CXL_HDM_DECODER_ENABLE BIT(1) > -#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) > -#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) > -#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) > -#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) > -#define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) > -#define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) > -#define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) > -#define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) > -#define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) > -#define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) > -#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) > -#define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) > -#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) > -#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) > -#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) > -#define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) > - > /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ > #define CXL_DECODER_MIN_GRANULARITY 256 > #define CXL_DECODER_MAX_ENCODED_IG 6 > diff --git a/include/uapi/cxl/cxl_regs.h b/include/uapi/cxl/cxl_regs.h > new file mode 100644 > index 000000000000..04bf790f0fdc > --- /dev/null > +++ b/include/uapi/cxl/cxl_regs.h > @@ -0,0 +1,58 @@ > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > +/* Copyright (c) 2026 NVIDIA Corporation & Affiliates */ > + > +#ifndef _UAPI_CXL_REGS_H_ > +#define _UAPI_CXL_REGS_H_ > + > +/* > + * CXL Component Register layout from the CXL specification. Kept in uapi so > a > + * VMM can consume the register offsets without a kernel header dependency. > + */ > + > +/* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ > +#define CXL_COMPONENT_REG_BLOCK_SIZE 0x10000 > + > +/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers */ > +#define CXL_CM_OFFSET 0x1000 > +#define CXL_CM_CAP_HDR_OFFSET 0x0 > +#define CXL_CM_CAP_HDR_ID_MASK 0xffff > +#define CM_CAP_HDR_CAP_ID 1 > +#define CXL_CM_CAP_HDR_VERSION_MASK 0xf0000 > +#define CM_CAP_HDR_CAP_VERSION 1 > +#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK 0xf00000 > +#define CM_CAP_HDR_CACHE_MEM_VERSION 1 > +#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK 0xff000000 > +#define CXL_CM_CAP_PTR_MASK 0xfff00000 > + > +#define CXL_CM_CAP_CAP_ID_RAS 0x2 > +#define CXL_CM_CAP_CAP_ID_HDM 0x5 > +#define CXL_CM_CAP_CAP_HDM_VERSION 1 > + > +/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ > +#define CXL_HDM_DECODER_CAP_OFFSET 0x0 > +#define CXL_HDM_DECODER_COUNT_MASK 0xf > +#define CXL_HDM_DECODER_TARGET_COUNT_MASK 0xf0 > +#define CXL_HDM_DECODER_INTERLEAVE_11_8 0x100 > +#define CXL_HDM_DECODER_INTERLEAVE_14_12 0x200 > +#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY 0x800 > +#define CXL_HDM_DECODER_INTERLEAVE_16_WAY 0x1000 > +#define CXL_HDM_DECODER_CTRL_OFFSET 0x4 > +#define CXL_HDM_DECODER_ENABLE 0x2 > +#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) > +#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) > +#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) > +#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) > +#define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) > +#define CXL_HDM_DECODER0_CTRL_IG_MASK 0xf > +#define CXL_HDM_DECODER0_CTRL_IW_MASK 0xf0 > +#define CXL_HDM_DECODER0_CTRL_LOCK 0x100 > +#define CXL_HDM_DECODER0_CTRL_COMMIT 0x200 > +#define CXL_HDM_DECODER0_CTRL_COMMITTED 0x400 > +#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR 0x800 > +#define CXL_HDM_DECODER0_CTRL_HOSTONLY 0x1000 > +#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) > +#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) > +#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) > +#define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) > + > +#endif /* _UAPI_CXL_REGS_H_ */
