On Sun, Feb 10, 2008 at 10:04:16PM -0700, Matthew Wilcox wrote:
> > "A disabled or non-existent device's configuration register space is
> > hidden. A disabled or non-existent device will return all ones for reads
> > and will drop writes just as if the cycle terminated with a Master Abort
> > on PCI."
>
> I'd like to thank Grant for pointing out to me that this is exactly what
> the write immediately above this is doing -- enabling device 8 to
> respond to config space cycles.
welcome.
...
> >From f565b65591a3f90a272b1d511e4ab1728861fe77 Mon Sep 17 00:00:00 2001
> From: Matthew Wilcox <[EMAIL PROTECTED]>
> Date: Sun, 10 Feb 2008 23:18:15 -0500
> Subject: [PATCH] Use proper abstractions in quirk_intel_irqbalance
>
> Since we may not have a pci_dev for the device we need to access, we can't
> use pci_read_config_word. But raw_pci_read is an internal implementation
> detail; it's better to use the architected pci_bus_read_config_word
> interface. Using PCI_DEVFN instead of a mysterious constant helps
> reassure everyone that we really do intend to access device 8.
>
> Signed-off-by: Matthew Wilcox <[EMAIL PROTECTED]>
> ---
> arch/x86/kernel/quirks.c | 9 ++++++---
> 1 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
> index 1941482..c47208f 100644
> --- a/arch/x86/kernel/quirks.c
> +++ b/arch/x86/kernel/quirks.c
> @@ -11,7 +11,7 @@
> static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
> {
> u8 config, rev;
> - u32 word;
> + u16 word;
>
> /* BIOS may enable hardware IRQ balancing for
> * E7520/E7320/E7525(revision ID 0x9 and below)
> @@ -26,8 +26,11 @@ static void __devinit quirk_intel_irqbalance(struct
> pci_dev *dev)
> pci_read_config_byte(dev, 0xf4, &config);
> pci_write_config_byte(dev, 0xf4, config|0x2);
Can you also add a comment which points at the Intel documentation?
http://download.intel.com/design/chipsets/datashts/30300702.pdf
Page 34 documents 0xf4 register.
And I just doubled checked that the 0xf4 register value is restored later
in the quirk (obvious when you look at the code but not from the patch).
> - /* read xTPR register */
> - raw_pci_read(0, 0, 0x40, 0x4c, 2, &word);
> + /*
> + * read xTPR register. We may not have a pci_dev for device 8
> + * because it might be hidden until the above write.
> + */
> + pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
Yeah, this should work even though we don't have a dev for it.
Acked-by: Grant Grundler <[EMAIL PROTECTED]>
thanks,
grant
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