On Thu, Jun 11, 2026 at 4:14 PM Guodong Xu <[email protected]> wrote: > > From: Andrew Jones <[email protected]> > > Add Ziccamoa, Ziccif, and Za64rs to riscv_isa_ext[] so they can be > parsed from devicetree/ACPI ISA strings. Ziccrse is already present > in cpufeature; this patch only adds its hwprobe exposure. > > Expose all four extensions via hwprobe through new bits in > RISCV_HWPROBE_KEY_IMA_EXT_1 (RISCV_HWPROBE_EXT_ZICCAMOA, _ZICCIF, > _ZICCRSE, _ZA64RS), so userspace can probe each of these > RVA23U64-mandatory extensions individually. > > Rationale for the validation dependencies added for Ziccamoa and Za64rs: > > 1) Ziccamoa depends on Zaamo. The RVA23 profile prose was updated > post-ratification to spell out the Zaamo reference: commit > 2b218613752d in riscv/riscv-profiles ("Improve description of > Ziccamoa (#224)") reworded the rva23-profile.adoc (and other profiles > that include Ziccamoa) text from "must support all atomics in A" to > "must support all atomics in the Zaamo extension" [1]. > > 2) Za64rs depends on Zalrsc. The unprivileged ISA manual src/zars.adoc, > integrated in commit ebe06adc22cd ("Integrate profiles as Volume III > (#2771)"), defines Za64rs as: "The Za64rs extension requires that the > reservation sets used by the instructions in the Zalrsc extension be > contiguous, naturally aligned, and at most 64 bytes in size" [2]. > > Link: > https://github.com/riscv/riscv-profiles/commit/2b218613752d63287286b5ae801b820cbd8cc10c > [1] > Link: > https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/zars.adoc [2] > Signed-off-by: Andrew Jones <[email protected]> > Signed-off-by: Guodong Xu <[email protected]>
Reviewed-by: Jesse Taube <[email protected]> > --- > v4: No change. > v3: Indent the added hwprobe.rst entries to match the normalized style; no > other change. > v2: > - Rebased to v7.1-rc2. > - Reworded subject and expanded commit message. > - Validation added for Ziccamoa depending on Zaamo and Za64rs depending > on Zalrsc. > --- > Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++ > arch/riscv/include/asm/hwcap.h | 3 +++ > arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++ > arch/riscv/kernel/cpufeature.c | 21 +++++++++++++++++++++ > arch/riscv/kernel/sys_hwprobe.c | 4 ++++ > 5 files changed, 48 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst > b/Documentation/arch/riscv/hwprobe.rst > index 49d9fb68632d0..893e1a1215d23 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -405,3 +405,19 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported, > as defined in the RISC-V Profiles specification starting from commit > b1d80660 ("Updated to ratified state.") > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is > supported, > + as defined in the RISC-V Profiles specification starting from commit > + b1d80660 ("Updated to ratified state.") > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported, > + as defined in the RISC-V Profiles specification starting from commit > + b1d80660 ("Updated to ratified state.") > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported, > + as defined in the RISC-V Profiles specification starting from commit > + b1d80660 ("Updated to ratified state.") > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported, > + as defined in the RISC-V Profiles specification starting from commit > + b1d80660 ("Updated to ratified state.") > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index e8f4a7dd96a93..0acb7a01ecc0f 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -113,6 +113,9 @@ > #define RISCV_ISA_EXT_ZICFILP 104 > #define RISCV_ISA_EXT_ZICFISS 105 > #define RISCV_ISA_EXT_ZICCLSM 106 > +#define RISCV_ISA_EXT_ZICCAMOA 107 > +#define RISCV_ISA_EXT_ZICCIF 108 > +#define RISCV_ISA_EXT_ZA64RS 109 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h > b/arch/riscv/include/uapi/asm/hwprobe.h > index 6819df159c51e..58d1e86e47ae7 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -117,6 +117,10 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_IMA_EXT_1 16 > #define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0) > #define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 1) > +#define RISCV_HWPROBE_EXT_ZICCAMOA (1ULL << 2) > +#define RISCV_HWPROBE_EXT_ZICCIF (1ULL << 3) > +#define RISCV_HWPROBE_EXT_ZICCRSE (1ULL << 4) > +#define RISCV_HWPROBE_EXT_ZA64RS (1ULL << 5) > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1fb595581adcf..b9538e69fa1b3 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -90,6 +90,24 @@ static int riscv_ext_f_depends(const struct > riscv_isa_ext_data *data, > return -EPROBE_DEFER; > } > > +static int riscv_ext_zaamo_depends(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZAAMO)) > + return 0; > + > + return -EPROBE_DEFER; > +} > + > +static int riscv_ext_zalrsc_depends(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZALRSC)) > + return 0; > + > + return -EPROBE_DEFER; > +} > + > static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, > const unsigned long *isa_bitmap) > { > @@ -502,6 +520,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, > riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate), > __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, > riscv_ext_zicbop_validate), > __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, > riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate), > + __RISCV_ISA_EXT_DATA_VALIDATE(ziccamoa, RISCV_ISA_EXT_ZICCAMOA, > riscv_ext_zaamo_depends), > + __RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF), > __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), > __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), > __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, > riscv_xlinuxenvcfg_exts, > @@ -516,6 +536,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), > + __RISCV_ISA_EXT_DATA_VALIDATE(za64rs, RISCV_ISA_EXT_ZA64RS, > riscv_ext_zalrsc_depends), > __RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO), > __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA), > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index 9cf62266f1890..b15ac9adf7920 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -206,6 +206,10 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair, > */ > EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing); > EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing); > + EXT_KEY(isainfo->isa, ZICCAMOA, pair->value, missing); > + EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing); > + EXT_KEY(isainfo->isa, ZICCRSE, pair->value, missing); > + EXT_KEY(isainfo->isa, ZA64RS, pair->value, missing); > } > > /* Now turn off reporting features if any CPU is missing it. */ > > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > [email protected] > http://lists.infradead.org/mailman/listinfo/linux-riscv
