On 05-06-2026 18:44, David Heidelberg wrote:
> + offset = 1;
> + break;
> + case V4L2_MBUS_CSI2_DPHY:
> + lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> + break;
> + default:
> + break;
> + }
>
> - for (i = 0; i < lane_cfg->num_data; i++)
> - lane_mask |= 1 << lane_cfg->data[i].pos;
> + for (int i = 0; i < lane_cfg->num_data; i++)
> + lane_mask |= BIT(lane_cfg->data[i].pos + offset);
>
> return lane_mask;
> }
csiphy_get_lane_mask() uses pos + offset but the 3PH hardware encodes lanes
at pos*2 (D-PHY) or pos*2+1 (C-PHY). Fix it as:
lane_mask |= BIT((lane_cfg->data[i].pos * 2) + offset);
> static bool csiphy_is_gen2(u32 version)
> {
> bool ret = false;
>
> @@ -1155,19 +1165,32 @@ static void csiphy_lanes_enable(struct csiphy_device
> *csiphy,
> struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
> struct csiphy_device_regs *regs = csiphy->regs;
> u8 settle_cnt;
> u8 val;
> int i;
>
> settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>
> - val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> - for (i = 0; i < c->num_data; i++)
> - val |= BIT(c->data[i].pos * 2);
> + val = 0;
> +
> + switch (c->phy_cfg) {
> + case V4L2_MBUS_CSI2_CPHY:
> + for (i = 0; i < c->num_data; i++)
> + val |= BIT((c->data[i].pos * 2) + 1);
> + break;
> + case V4L2_MBUS_CSI2_DPHY:
> + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> +
> + for (i = 0; i < c->num_data; i++)
> + val |= BIT(c->data[i].pos * 2);
> + break;
> + default:
> + WARN_ONCE(1, "Unsupported bus type %d!\n", c->phy_cfg);
> + }
Also, with above fix in place, lanes_enable() can reuse csiphy_get_lane_mask()
instead of open-coding the same logic.
---
Regards,
Nihal Kumar Gupta
