rdmsrl() is a deprecated synonym for rdmsrq(). Switch its users to rdmsrq().
Signed-off-by: Juergen Gross <[email protected]> --- arch/x86/events/amd/uncore.c | 2 +- arch/x86/kernel/cpu/resctrl/monitor.c | 2 +- drivers/hv/mshv_vtl_main.c | 2 +- drivers/idle/intel_idle.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index dd956cfcadef..98ef4bf9911a 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -966,7 +966,7 @@ static void amd_uncore_umc_read(struct perf_event *event) * UMC counters do not have RDPMC assignments. Read counts directly * from the corresponding PERF_CTR. */ - rdmsrl(hwc->event_base, new); + rdmsrq(hwc->event_base, new); /* * Unlike the other uncore counters, UMC counters saturate and set the diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index 59215fef3924..c5ed0bc1f831 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -301,7 +301,7 @@ static int __cntr_id_read(u32 cntr_id, u64 *val) * is set if the counter data is unavailable. */ wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id); - rdmsrl(MSR_IA32_QM_CTR, msr_val); + rdmsrq(MSR_IA32_QM_CTR, msr_val); if (msr_val & RMID_VAL_ERROR) return -EIO; diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c index c19400701467..f5d27f28d6ad 100644 --- a/drivers/hv/mshv_vtl_main.c +++ b/drivers/hv/mshv_vtl_main.c @@ -598,7 +598,7 @@ static int mshv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set) if (set) wrmsrl(reg_table[i].msr_addr, *reg64); else - rdmsrl(reg_table[i].msr_addr, *reg64); + rdmsrq(reg_table[i].msr_addr, *reg64); } return 0; } diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index f49354e37777..15c698291b32 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -2370,7 +2370,7 @@ static void intel_c1_demotion_toggle(void *enable) { unsigned long long msr_val; - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val); + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val); /* * Enable/disable C1 undemotion along with C1 demotion, as this is the * most sensible configuration in general. @@ -2410,7 +2410,7 @@ static ssize_t intel_c1_demotion_show(struct device *dev, * Read the MSR value for a CPU and assume it is the same for all CPUs. Any other * configuration would be a BIOS bug. */ - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val); + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val); return sysfs_emit(buf, "%d\n", !!(msr_val & NHM_C1_AUTO_DEMOTE)); } static DEVICE_ATTR_RW(intel_c1_demotion); -- 2.54.0
