From: David Heidelberg <[email protected]> The IMX355 sensor supports multiple external clock frequencies, including 19.2 MHz and 24 MHz. The driver currently supports only fixed 19.2 MHz input clock.
Refactor the clock handling to make the PLL configuration dependent on the external clock frequency and add support for 24 MHz. Introduce a table of clock parameter sets and program the corresponding EXTCLK frequency and PLL multipliers to maintain consistent internal VCO frequencies across supported inputs. The PLL settings are adjusted so that: - VT VCO remains at 1152 MHz - OP VCO remains at 720 MHz This preserves existing timing characteristics while allowing systems using a 24 MHz clock to operate correctly. No functional change for existing 19.2 MHz users. Assisted-by: Claude:claude-opus-4-6 Reviewed-by: Dave Stevenson <[email protected]> Tested-by: Dave Stevenson <[email protected]> Tested-by: Richard Acayan <[email protected]> # Pixel 3a Signed-off-by: David Heidelberg <[email protected]> --- Known users: Pixel 3 and 3a. --- Changes in v2: - Adapt to follow the naming used in ccs-regs.h. - Gathered R-b/T-bs. - Link to v1: https://lore.kernel.org/r/[email protected] --- drivers/media/i2c/imx355.c | 114 +++++++++++++++++++++------------------------ 1 file changed, 54 insertions(+), 60 deletions(-) diff --git a/drivers/media/i2c/imx355.c b/drivers/media/i2c/imx355.c index 27a5c212a527f..48300804f53ee 100644 --- a/drivers/media/i2c/imx355.c +++ b/drivers/media/i2c/imx355.c @@ -20,16 +20,21 @@ #define IMX355_REG_MODE_SELECT 0x0100 #define IMX355_MODE_STANDBY 0x00 #define IMX355_MODE_STREAMING 0x01 /* Chip ID */ #define IMX355_REG_CHIP_ID 0x0016 #define IMX355_CHIP_ID 0x0355 +/* PLL registers that depend on the external clock frequency */ +#define IMX355_R_EXTCLK_FREQUENCY_MHZ 0x0136 +#define IMX355_R_PLL_MULTIPLIER 0x0306 +#define IMX355_R_OP_PLL_MULTIPLIER 0x030e + /* V_TIMING internal */ #define IMX355_REG_FLL 0x0340 #define IMX355_FLL_MAX 0xffff /* Exposure control */ #define IMX355_REG_EXPOSURE 0x0202 #define IMX355_EXPOSURE_MIN 1 #define IMX355_EXPOSURE_STEP 1 @@ -58,17 +63,16 @@ #define IMX355_TEST_PATTERN_GRAY_COLOR_BARS 3 #define IMX355_TEST_PATTERN_PN9 4 /* Flip Control */ #define IMX355_REG_ORIENTATION 0x0101 /* default link frequency and external clock */ #define IMX355_LINK_FREQ_DEFAULT 360000000LL -#define IMX355_EXT_CLK 19200000 #define IMX355_LINK_FREQ_INDEX 0 /* number of data lanes */ #define IMX355_DATA_LANES 4 struct imx355_reg { u16 address; u8 val; @@ -95,16 +99,43 @@ struct imx355_mode { /* index of link frequency */ u32 link_freq_index; /* Default register values */ struct imx355_reg_list reg_list; }; +struct imx355_clk_params { + u32 ext_clk; + u16 extclk_freq; /* External clock (MHz) in 8.8 fixed point) */ + u16 pll_vt_mpy; /* VT system PLL multiplier */ + u16 pll_op_mpy; /* OP system PLL multiplier */ +}; + +/* + * All modes use the same PLL dividers (PREPLLCK_VT_DIV=2, PREPLLCK_OP_DIV=2), + * so the multipliers are adjusted to produce the same VCO frequencies: + * VT VCO = 1152 MHz, OP VCO = 720 MHz + */ +static const struct imx355_clk_params imx355_clk_params[] = { + { + .ext_clk = 19200000, + .extclk_freq = 0x1333, /* 19.2 MHz */ + .pll_vt_mpy = 120, /* 19.2 / 2 * 120 = 1152 MHz */ + .pll_op_mpy = 75, /* 19.2 / 2 * 75 = 720 MHz */ + }, + { + .ext_clk = 24000000, + .extclk_freq = 0x1800, /* 24.0 MHz */ + .pll_vt_mpy = 96, /* 24.0 / 2 * 96 = 1152 MHz */ + .pll_op_mpy = 60, /* 24.0 / 2 * 60 = 720 MHz */ + }, +}; + struct imx355_hwcfg { unsigned long link_freq_bitmap; }; struct imx355 { struct device *dev; struct clk *clk; @@ -120,16 +151,17 @@ struct imx355 { struct v4l2_ctrl *exposure; struct v4l2_ctrl *vflip; struct v4l2_ctrl *hflip; /* Current mode */ const struct imx355_mode *cur_mode; struct imx355_hwcfg *hwcfg; + const struct imx355_clk_params *clk_params; /* * Mutex for serialized access: * Protect sensor set pad format and start/stop streaming safely. * Protect access to sensor v4l2 controls. */ struct mutex mutex; @@ -139,18 +171,16 @@ struct imx355 { static const struct regulator_bulk_data imx355_supplies[] = { { .supply = "avdd" }, { .supply = "dvdd" }, { .supply = "dovdd" }, }; static const struct imx355_reg imx355_global_regs[] = { - { 0x0136, 0x13 }, - { 0x0137, 0x33 }, { 0x304e, 0x03 }, { 0x4348, 0x16 }, { 0x4350, 0x19 }, { 0x4408, 0x0a }, { 0x440c, 0x0b }, { 0x4411, 0x5f }, { 0x4412, 0x2c }, { 0x4623, 0x00 }, @@ -226,22 +256,18 @@ static const struct imx355_reg mode_3268x2448_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x0c }, { 0x034d, 0xc4 }, { 0x034e, 0x09 }, { 0x034f, 0x90 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -275,22 +301,18 @@ static const struct imx355_reg mode_3264x2448_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x0c }, { 0x034d, 0xc0 }, { 0x034e, 0x09 }, { 0x034f, 0x90 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -324,22 +346,18 @@ static const struct imx355_reg mode_3280x2464_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x0c }, { 0x034d, 0xd0 }, { 0x034e, 0x09 }, { 0x034f, 0xa0 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -373,22 +391,18 @@ static const struct imx355_reg mode_1940x1096_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x07 }, { 0x034d, 0x94 }, { 0x034e, 0x04 }, { 0x034f, 0x48 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -422,22 +436,18 @@ static const struct imx355_reg mode_1936x1096_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x07 }, { 0x034d, 0x90 }, { 0x034e, 0x04 }, { 0x034f, 0x48 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -471,22 +481,18 @@ static const struct imx355_reg mode_1924x1080_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x07 }, { 0x034d, 0x84 }, { 0x034e, 0x04 }, { 0x034f, 0x38 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -520,22 +526,18 @@ static const struct imx355_reg mode_1920x1080_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x07 }, { 0x034d, 0x80 }, { 0x034e, 0x04 }, { 0x034f, 0x38 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -569,22 +571,18 @@ static const struct imx355_reg mode_1640x1232_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x06 }, { 0x034d, 0x68 }, { 0x034e, 0x04 }, { 0x034f, 0xd0 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -618,22 +616,18 @@ static const struct imx355_reg mode_1640x922_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x06 }, { 0x034d, 0x68 }, { 0x034e, 0x03 }, { 0x034f, 0x9a }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -667,22 +661,18 @@ static const struct imx355_reg mode_1300x736_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x05 }, { 0x034d, 0x14 }, { 0x034e, 0x02 }, { 0x034f, 0xe0 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -716,22 +706,18 @@ static const struct imx355_reg mode_1296x736_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x05 }, { 0x034d, 0x10 }, { 0x034e, 0x02 }, { 0x034f, 0xe0 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -765,22 +751,18 @@ static const struct imx355_reg mode_1284x720_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x05 }, { 0x034d, 0x04 }, { 0x034e, 0x02 }, { 0x034f, 0xd0 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -814,22 +796,18 @@ static const struct imx355_reg mode_1280x720_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x05 }, { 0x034d, 0x00 }, { 0x034e, 0x02 }, { 0x034f, 0xd0 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x00 }, { 0x0701, 0x10 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -863,22 +841,18 @@ static const struct imx355_reg mode_820x616_regs[] = { { 0x0902, 0x00 }, { 0x034c, 0x03 }, { 0x034d, 0x34 }, { 0x034e, 0x02 }, { 0x034f, 0x68 }, { 0x0301, 0x05 }, { 0x0303, 0x01 }, { 0x0305, 0x02 }, - { 0x0306, 0x00 }, - { 0x0307, 0x78 }, { 0x030b, 0x01 }, { 0x030d, 0x02 }, - { 0x030e, 0x00 }, - { 0x030f, 0x4b }, { 0x0310, 0x00 }, { 0x0700, 0x02 }, { 0x0701, 0x78 }, { 0x0820, 0x0b }, { 0x0821, 0x40 }, { 0x3088, 0x04 }, { 0x6813, 0x02 }, { 0x6835, 0x07 }, @@ -1417,16 +1391,30 @@ static int imx355_start_streaming(struct imx355 *imx355) /* Apply default values of current mode */ reg_list = &imx355->cur_mode->reg_list; ret = imx355_write_regs(imx355, reg_list->regs, reg_list->num_of_regs); if (ret) { dev_err(imx355->dev, "failed to set mode"); return ret; } + /* Set PLL registers for the external clock frequency */ + ret = imx355_write_reg(imx355, IMX355_R_EXTCLK_FREQUENCY_MHZ, 2, + imx355->clk_params->extclk_freq); + if (ret) + return ret; + ret = imx355_write_reg(imx355, IMX355_R_PLL_MULTIPLIER, 2, + imx355->clk_params->pll_vt_mpy); + if (ret) + return ret; + ret = imx355_write_reg(imx355, IMX355_R_OP_PLL_MULTIPLIER, 2, + imx355->clk_params->pll_op_mpy); + if (ret) + return ret; + /* set digital gain control to all color mode */ ret = imx355_write_reg(imx355, IMX355_REG_DPGA_USE_GLOBAL_GAIN, 1, 1); if (ret) return ret; /* Apply customized values from user */ ret = __v4l2_ctrl_handler_setup(imx355->sd.ctrl_handler); if (ret) @@ -1744,17 +1732,23 @@ static int imx355_probe(struct i2c_client *client) mutex_init(&imx355->mutex); imx355->clk = devm_v4l2_sensor_clk_get(imx355->dev, NULL); if (IS_ERR(imx355->clk)) return dev_err_probe(imx355->dev, PTR_ERR(imx355->clk), "failed to get clock\n"); freq = clk_get_rate(imx355->clk); - if (freq != IMX355_EXT_CLK) + for (unsigned int i = 0; i < ARRAY_SIZE(imx355_clk_params); i++) { + if (freq == imx355_clk_params[i].ext_clk) { + imx355->clk_params = &imx355_clk_params[i]; + break; + } + } + if (!imx355->clk_params) return dev_err_probe(imx355->dev, -EINVAL, "external clock %lu is not supported\n", freq); ret = devm_regulator_bulk_get_const(imx355->dev, ARRAY_SIZE(imx355_supplies), imx355_supplies, &imx355->supplies); --- base-commit: e43ffb69e0438cddd72aaa30898b4dc446f664f8 change-id: 20260414-imx355-24mhz-b8ccfab3adfb Best regards, -- David Heidelberg <[email protected]>
