On Mon, Mar 24, 2025 at 05:40:30PM -0700, Atish Patra wrote:
> Currently, the sbi_pmu_test continues if the exception type is illegal
> instruction because access to hpmcounter will generate that. However, we
> may get illegal for other reasons as well which should result in test
> assertion.
>
> Use the stval to decode the exact type of instructions and which csrs are
> being accessed if it is csr access instructions. Assert in all cases
> except if it is a csr access instructions that access valid PMU related
> registers.
>
> Signed-off-by: Atish Patra <ati...@rivosinc.com>
> ---
> tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 32
> ++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
> b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
> index 03406de4989d..11bde69b5238 100644
> --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
> +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
> @@ -128,11 +128,43 @@ static void stop_counter(unsigned long counter,
> unsigned long stop_flags)
> "Unable to stop counter %ld error %ld\n", counter,
> ret.error);
> }
>
> +#define INSN_OPCODE_MASK 0x007c
> +#define INSN_OPCODE_SHIFT 2
> +#define INSN_OPCODE_SYSTEM 28
> +
> +#define INSN_MASK_FUNCT3 0x7000
> +#define INSN_SHIFT_FUNCT3 12
> +
> +#define INSN_CSR_MASK 0xfff00000
> +#define INSN_CSR_SHIFT 20
> +
> +#define GET_RM(insn) (((insn) & INSN_MASK_FUNCT3) >>
> INSN_SHIFT_FUNCT3)
> +#define GET_CSR_NUM(insn) (((insn) & INSN_CSR_MASK) >> INSN_CSR_SHIFT)
It'd be good to put these macros in include/riscv/processor.h or some new
include/riscv/ header to be shared with other tests that may want to
decode stval.
Thanks,
drew
> +
> static void guest_illegal_exception_handler(struct ex_regs *regs)
> {
> + unsigned long insn;
> + int opcode, csr_num, funct3;
> +
> __GUEST_ASSERT(regs->cause == EXC_INST_ILLEGAL,
> "Unexpected exception handler %lx\n", regs->cause);
>
> + insn = regs->stval;
> + opcode = (insn & INSN_OPCODE_MASK) >> INSN_OPCODE_SHIFT;
> + __GUEST_ASSERT(opcode == INSN_OPCODE_SYSTEM,
> + "Unexpected instruction with opcode 0x%x insn 0x%lx\n",
> opcode, insn);
> +
> + csr_num = GET_CSR_NUM(insn);
> + funct3 = GET_RM(insn);
> + /* Validate if it is a CSR read/write operation */
> + __GUEST_ASSERT(funct3 <= 7 && (funct3 != 0 || funct3 != 4),
> + "Unexpected system opcode with funct3 0x%x csr_num
> 0x%x\n",
> + funct3, csr_num);
> +
> + /* Validate if it is a HPMCOUNTER CSR operation */
> + __GUEST_ASSERT(csr_num == CSR_CYCLE || csr_num <= CSR_HPMCOUNTER31,
> + "Unexpected csr_num 0x%x\n", csr_num);
> +
> illegal_handler_invoked = true;
> /* skip the trapping instruction */
> regs->epc += 4;
>
> --
> 2.43.0
>
>
> --
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