On Tue, Mar 25, 2025 at 6:10 AM Atish Patra <ati...@rivosinc.com> wrote:
>
> Save stval during exception handling so that it can be decoded to
> figure out the details of exception type.
>
> Signed-off-by: Atish Patra <ati...@rivosinc.com>
LGTM.
Reviewed-by: Anup Patel <a...@brainfault.org>
Regards,
Anup
> ---
> tools/testing/selftests/kvm/include/riscv/processor.h | 1 +
> tools/testing/selftests/kvm/lib/riscv/handlers.S | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h
> b/tools/testing/selftests/kvm/include/riscv/processor.h
> index 5f389166338c..f4a7d64fbe9a 100644
> --- a/tools/testing/selftests/kvm/include/riscv/processor.h
> +++ b/tools/testing/selftests/kvm/include/riscv/processor.h
> @@ -95,6 +95,7 @@ struct ex_regs {
> unsigned long epc;
> unsigned long status;
> unsigned long cause;
> + unsigned long stval;
> };
>
> #define NR_VECTORS 2
> diff --git a/tools/testing/selftests/kvm/lib/riscv/handlers.S
> b/tools/testing/selftests/kvm/lib/riscv/handlers.S
> index aa0abd3f35bb..2884c1e8939b 100644
> --- a/tools/testing/selftests/kvm/lib/riscv/handlers.S
> +++ b/tools/testing/selftests/kvm/lib/riscv/handlers.S
> @@ -45,9 +45,11 @@
> csrr s0, CSR_SEPC
> csrr s1, CSR_SSTATUS
> csrr s2, CSR_SCAUSE
> + csrr s3, CSR_STVAL
> sd s0, 248(sp)
> sd s1, 256(sp)
> sd s2, 264(sp)
> + sd s3, 272(sp)
> .endm
>
> .macro restore_context
>
> --
> 2.43.0
>
