The test verifies reads and writes for MSR registers with different access
level.
Signed-off-by: Sagi Shahar <sa...@google.com>
---
.../selftests/kvm/include/x86/tdx/tdx.h | 4 +
tools/testing/selftests/kvm/lib/x86/tdx/tdx.c | 27 +++
tools/testing/selftests/kvm/x86/tdx_vm_test.c | 193 +++++++++++++++++-
3 files changed, 223 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/kvm/include/x86/tdx/tdx.h
b/tools/testing/selftests/kvm/include/x86/tdx/tdx.h
index 97ceb90c8792..56359a8c4c19 100644
--- a/tools/testing/selftests/kvm/include/x86/tdx/tdx.h
+++ b/tools/testing/selftests/kvm/include/x86/tdx/tdx.h
@@ -10,10 +10,14 @@
#define TDG_VP_VMCALL_REPORT_FATAL_ERROR 0x10003
#define TDG_VP_VMCALL_INSTRUCTION_IO 30
+#define TDG_VP_VMCALL_INSTRUCTION_RDMSR 31
+#define TDG_VP_VMCALL_INSTRUCTION_WRMSR 32
uint64_t tdg_vp_vmcall_instruction_io(uint64_t port, uint64_t size,
uint64_t write, uint64_t *data);
void tdg_vp_vmcall_report_fatal_error(uint64_t error_code, uint64_t data_gpa);
uint64_t tdg_vp_vmcall_get_td_vmcall_info(uint64_t *r11, uint64_t *r12,
uint64_t *r13, uint64_t *r14);
+uint64_t tdg_vp_vmcall_instruction_rdmsr(uint64_t index, uint64_t *ret_value);
+uint64_t tdg_vp_vmcall_instruction_wrmsr(uint64_t index, uint64_t value);
#endif // SELFTEST_TDX_TDX_H
diff --git a/tools/testing/selftests/kvm/lib/x86/tdx/tdx.c
b/tools/testing/selftests/kvm/lib/x86/tdx/tdx.c
index 5105dfae0e9e..99ec45a5a657 100644
--- a/tools/testing/selftests/kvm/lib/x86/tdx/tdx.c
+++ b/tools/testing/selftests/kvm/lib/x86/tdx/tdx.c
@@ -66,3 +66,30 @@ uint64_t tdg_vp_vmcall_get_td_vmcall_info(uint64_t *r11,
uint64_t *r12,
return ret;
}
+
+uint64_t tdg_vp_vmcall_instruction_rdmsr(uint64_t index, uint64_t *ret_value)
+{
+ struct tdx_hypercall_args args = {
+ .r11 = TDG_VP_VMCALL_INSTRUCTION_RDMSR,
+ .r12 = index,
+ };
+ uint64_t ret;
+
+ ret = __tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT);
+
+ if (ret_value)
+ *ret_value = args.r11;
+
+ return ret;
+}
+
+uint64_t tdg_vp_vmcall_instruction_wrmsr(uint64_t index, uint64_t value)
+{
+ struct tdx_hypercall_args args = {
+ .r11 = TDG_VP_VMCALL_INSTRUCTION_WRMSR,
+ .r12 = index,
+ .r13 = value,
+ };
+
+ return __tdx_hypercall(&args, 0);
+}
diff --git a/tools/testing/selftests/kvm/x86/tdx_vm_test.c
b/tools/testing/selftests/kvm/x86/tdx_vm_test.c
index ae5749e5c605..079ac266a44e 100644
--- a/tools/testing/selftests/kvm/x86/tdx_vm_test.c
+++ b/tools/testing/selftests/kvm/x86/tdx_vm_test.c
@@ -455,6 +455,193 @@ void verify_guest_reads(void)
printf("\t ... PASSED\n");
}
+/*
+ * Define a filter which denies all MSR access except the following:
+ * MSR_X2APIC_APIC_ICR: Allow read/write access (allowed by default)
+ * MSR_IA32_MISC_ENABLE: Allow read access
+ * MSR_IA32_POWER_CTL: Allow write access
+ */
+#define MSR_X2APIC_APIC_ICR 0x830
+static u64 tdx_msr_test_allow_bits = ~0ULL;
+struct kvm_msr_filter tdx_msr_test_filter = {
+ .flags = KVM_MSR_FILTER_DEFAULT_DENY,
+ .ranges = {
+ {
+ .flags = KVM_MSR_FILTER_READ,
+ .nmsrs = 1,
+ .base = MSR_IA32_MISC_ENABLE,
+ .bitmap = (uint8_t *)&tdx_msr_test_allow_bits,
+ }, {
+ .flags = KVM_MSR_FILTER_WRITE,
+ .nmsrs = 1,
+ .base = MSR_IA32_POWER_CTL,
+ .bitmap = (uint8_t *)&tdx_msr_test_allow_bits,
+ },
+ },
+};
+
+/*
+ * Verifies MSR read functionality.
+ */
+void guest_msr_read(void)
+{
+ uint64_t data;
+ uint64_t ret;
+
+ ret = tdg_vp_vmcall_instruction_rdmsr(MSR_X2APIC_APIC_ICR, &data);
+ tdx_assert_error(ret);
+
+ ret = tdx_test_report_64bit_to_user_space(data);
+ tdx_assert_error(ret);
+
+ ret = tdg_vp_vmcall_instruction_rdmsr(MSR_IA32_MISC_ENABLE, &data);
+ tdx_assert_error(ret);
+
+ ret = tdx_test_report_64bit_to_user_space(data);
+ tdx_assert_error(ret);
+
+ /* Expect this call to fail since MSR_IA32_POWER_CTL is write only */
+ ret = tdg_vp_vmcall_instruction_rdmsr(MSR_IA32_POWER_CTL, &data);
+ if (ret) {
+ ret = tdx_test_report_64bit_to_user_space(ret);
+ tdx_assert_error(ret);
+ } else {
+ tdx_test_fatal(-99);
+ }
+
+ tdx_test_success();
+}
+
+void verify_guest_msr_reads(void)
+{
+ struct kvm_vcpu *vcpu;
+ struct kvm_vm *vm;
+ uint64_t data;
+ int ret;
+
+ vm = td_create();
+ td_initialize(vm, VM_MEM_SRC_ANONYMOUS, 0);
+
+ /*
+ * Set explicit MSR filter map to control access to the MSR registers
+ * used in the test.
+ */
+ printf("\t ... Setting test MSR filter\n");
+ ret = kvm_check_cap(KVM_CAP_X86_MSR_FILTER);
+ TEST_ASSERT(ret, "KVM_CAP_X86_MSR_FILTER is unavailable");
+
+ ret = ioctl(vm->fd, KVM_X86_SET_MSR_FILTER, &tdx_msr_test_filter);
+ TEST_ASSERT(ret == 0,
+ "KVM_X86_SET_MSR_FILTER failed, ret: %i errno: %i (%s)",
+ ret, errno, strerror(errno));
+
+ vcpu = td_vcpu_add(vm, 0, guest_msr_read);
+ td_finalize(vm);
+
+ printf("Verifying guest msr reads:\n");
+
+ printf("\t ... Setting test MSR values\n");
+ /* Write arbitrary to the MSRs. */
+ vcpu_set_msr(vcpu, MSR_X2APIC_APIC_ICR, 4);
+ vcpu_set_msr(vcpu, MSR_IA32_MISC_ENABLE, 5);
+ vcpu_set_msr(vcpu, MSR_IA32_POWER_CTL, 6);
+
+ printf("\t ... Running guest\n");
+ tdx_run(vcpu);
+ data = tdx_test_read_64bit_report_from_guest(vcpu);
+ TEST_ASSERT_EQ(data, 4);
+
+ tdx_run(vcpu);
+ data = tdx_test_read_64bit_report_from_guest(vcpu);
+ TEST_ASSERT_EQ(data, 5);
+
+ tdx_run(vcpu);
+ data = tdx_test_read_64bit_report_from_guest(vcpu);
+ TEST_ASSERT_EQ(data, TDG_VP_VMCALL_INVALID_OPERAND);
+
+ tdx_run(vcpu);
+ tdx_test_assert_success(vcpu);
+
+ kvm_vm_free(vm);
+ printf("\t ... PASSED\n");
+}
+
+/*
+ * Verifies MSR write functionality.
+ */
+void guest_msr_write(void)
+{
+ uint64_t ret;
+
+ ret = tdg_vp_vmcall_instruction_wrmsr(MSR_X2APIC_APIC_ICR, 4);
+ tdx_assert_error(ret);
+
+ /* Expect this call to fail since MSR_IA32_MISC_ENABLE is read only */
+ ret = tdg_vp_vmcall_instruction_wrmsr(MSR_IA32_MISC_ENABLE, 5);
+ if (ret) {
+ ret = tdx_test_report_64bit_to_user_space(ret);
+ tdx_assert_error(ret);
+ } else {
+ tdx_test_fatal(-99);
+ }
+
+ ret = tdg_vp_vmcall_instruction_wrmsr(MSR_IA32_POWER_CTL, 6);
+ tdx_assert_error(ret);
+
+ tdx_test_success();
+}
+
+void verify_guest_msr_writes(void)
+{
+ uint64_t ia32_misc_enable_val;
+ struct kvm_vcpu *vcpu;
+ struct kvm_vm *vm;
+ uint64_t data;
+ int ret;
+
+ vm = td_create();
+ td_initialize(vm, VM_MEM_SRC_ANONYMOUS, 0);
+
+ /*
+ * Set explicit MSR filter map to control access to the MSR registers
+ * used in the test.
+ */
+ printf("\t ... Setting test MSR filter\n");
+ ret = kvm_check_cap(KVM_CAP_X86_MSR_FILTER);
+ TEST_ASSERT(ret, "KVM_CAP_X86_MSR_FILTER is unavailable");
+
+ ret = ioctl(vm->fd, KVM_X86_SET_MSR_FILTER, &tdx_msr_test_filter);
+ TEST_ASSERT(ret == 0,
+ "KVM_X86_SET_MSR_FILTER failed, ret: %i errno: %i (%s)",
+ ret, errno, strerror(errno));
+
+ vcpu = td_vcpu_add(vm, 0, guest_msr_write);
+ td_finalize(vm);
+
+ ia32_misc_enable_val = vcpu_get_msr(vcpu, MSR_IA32_MISC_ENABLE);
+
+ printf("Verifying guest msr writes:\n");
+
+ printf("\t ... Running guest\n");
+ /* Only the write to MSR_IA32_MISC_ENABLE should trigger an exit */
+ tdx_run(vcpu);
+ data = tdx_test_read_64bit_report_from_guest(vcpu);
+ TEST_ASSERT_EQ(data, TDG_VP_VMCALL_INVALID_OPERAND);
+
+ tdx_run(vcpu);
+ tdx_test_assert_success(vcpu);
+
+ printf("\t ... Verifying MSR values written by guest\n");
+
+ TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_X2APIC_APIC_ICR), 4);
+ TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_IA32_MISC_ENABLE),
+ ia32_misc_enable_val);
+ TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_IA32_POWER_CTL), 6);
+
+ kvm_vm_free(vm);
+ printf("\t ... PASSED\n");
+}
+
int main(int argc, char **argv)
{
ksft_print_header();
@@ -462,7 +649,7 @@ int main(int argc, char **argv)
if (!is_tdx_enabled())
ksft_exit_skip("TDX is not supported by the KVM. Exiting.\n");
- ksft_set_plan(7);
+ ksft_set_plan(9);
ksft_test_result(!run_in_new_process(&verify_td_lifecycle),
"verify_td_lifecycle\n");
ksft_test_result(!run_in_new_process(&verify_report_fatal_error),
@@ -477,6 +664,10 @@ int main(int argc, char **argv)
"verify_guest_writes\n");
ksft_test_result(!run_in_new_process(&verify_guest_reads),
"verify_guest_reads\n");
+ ksft_test_result(!run_in_new_process(&verify_guest_msr_writes),
+ "verify_guest_msr_writes\n");
+ ksft_test_result(!run_in_new_process(&verify_guest_msr_reads),
+ "verify_guest_msr_reads\n");
ksft_finished();
return 0;
--
2.49.0.504.g3bcea36a83-goog
