Prevent tracing to start if aux_paused.

Implement support for PERF_EF_PAUSE / PERF_EF_RESUME. When aux_paused, stop
tracing. When not aux_paused, only start tracing if it isn't currently
meant to be stopped.

Signed-off-by: Adrian Hunter <adrian.hun...@intel.com>
Reviewed-by: Andi Kleen <a...@linux.intel.com>
---


Changes in V12:
        Rebase on current tip plus patch set "KVM: x86: Fix Intel PT Host/Guest
        mode when host tracing"

Changes in V9:
        Add more comments and barriers for resume_allowed and
        pause_allowed
        Always use WRITE_ONCE with resume_allowed


 arch/x86/events/intel/pt.c | 69 ++++++++++++++++++++++++++++++++++++--
 arch/x86/events/intel/pt.h |  4 +++
 2 files changed, 70 insertions(+), 3 deletions(-)

diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index d9469d2d6aa6..b6cfca251c07 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -418,6 +418,9 @@ static void pt_config_start(struct perf_event *event)
        struct pt *pt = this_cpu_ptr(&pt_ctx);
        u64 ctl = event->hw.aux_config;
 
+       if (READ_ONCE(event->hw.aux_paused))
+               return;
+
        ctl |= RTIT_CTL_TRACEEN;
        if (READ_ONCE(pt->vmx_on))
                perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
@@ -539,11 +542,23 @@ static void pt_config(struct perf_event *event)
 
        event->hw.aux_config = reg;
 
+       /*
+        * Allow resume before starting so as not to overwrite a value set by a
+        * PMI.
+        */
+       barrier();
+       WRITE_ONCE(pt->resume_allowed, 1);
        /* Configuration is complete, it is now OK to handle an NMI */
        barrier();
        WRITE_ONCE(pt->handle_nmi, 1);
-
+       barrier();
        pt_config_start(event);
+       barrier();
+       /*
+        * Allow pause after starting so its pt_config_stop() doesn't race with
+        * pt_config_start().
+        */
+       WRITE_ONCE(pt->pause_allowed, 1);
 }
 
 static void pt_config_stop(struct perf_event *event)
@@ -1526,6 +1541,7 @@ void intel_pt_interrupt(void)
                buf = perf_aux_output_begin(&pt->handle, event);
                if (!buf) {
                        event->hw.state = PERF_HES_STOPPED;
+                       WRITE_ONCE(pt->resume_allowed, 0);
                        return;
                }
 
@@ -1534,6 +1550,7 @@ void intel_pt_interrupt(void)
                ret = pt_buffer_reset_markers(buf, &pt->handle);
                if (ret) {
                        perf_aux_output_end(&pt->handle, 0);
+                       WRITE_ONCE(pt->resume_allowed, 0);
                        return;
                }
 
@@ -1588,6 +1605,26 @@ static void pt_event_start(struct perf_event *event, int 
mode)
        struct pt *pt = this_cpu_ptr(&pt_ctx);
        struct pt_buffer *buf;
 
+       if (mode & PERF_EF_RESUME) {
+               if (READ_ONCE(pt->resume_allowed)) {
+                       u64 status;
+
+                       /*
+                        * Only if the trace is not active and the error and
+                        * stopped bits are clear, is it safe to start, but a
+                        * PMI might have just cleared these, so resume_allowed
+                        * must be checked again also.
+                        */
+                       rdmsrl(MSR_IA32_RTIT_STATUS, status);
+                       if (!(status & (RTIT_STATUS_TRIGGEREN |
+                                       RTIT_STATUS_ERROR |
+                                       RTIT_STATUS_STOPPED)) &&
+                          READ_ONCE(pt->resume_allowed))
+                               pt_config_start(event);
+               }
+               return;
+       }
+
        buf = perf_aux_output_begin(&pt->handle, event);
        if (!buf)
                goto fail_stop;
@@ -1615,6 +1652,12 @@ static void pt_event_stop(struct perf_event *event, int 
mode)
 {
        struct pt *pt = this_cpu_ptr(&pt_ctx);
 
+       if (mode & PERF_EF_PAUSE) {
+               if (READ_ONCE(pt->pause_allowed))
+                       pt_config_stop(event);
+               return;
+       }
+
        /*
         * Protect against the PMI racing with disabling wrmsr,
         * see comment in intel_pt_interrupt().
@@ -1622,6 +1665,15 @@ static void pt_event_stop(struct perf_event *event, int 
mode)
        WRITE_ONCE(pt->handle_nmi, 0);
        barrier();
 
+       /*
+        * Prevent a resume from attempting to restart tracing, or a pause
+        * during a subsequent start. Do this after clearing handle_nmi so that
+        * pt_event_snapshot_aux() will not re-allow them.
+        */
+       WRITE_ONCE(pt->pause_allowed, 0);
+       WRITE_ONCE(pt->resume_allowed, 0);
+       barrier();
+
        pt_config_stop(event);
 
        if (event->hw.state == PERF_HES_STOPPED)
@@ -1787,6 +1839,10 @@ static long pt_event_snapshot_aux(struct perf_event 
*event,
        if (WARN_ON_ONCE(!buf->snapshot))
                return 0;
 
+       /* Prevent pause/resume from attempting to start/stop tracing */
+       WRITE_ONCE(pt->pause_allowed, 0);
+       WRITE_ONCE(pt->resume_allowed, 0);
+       barrier();
        /*
         * There is no PT interrupt in this mode, so stop the trace and it will
         * remain stopped while the buffer is copied.
@@ -1806,8 +1862,13 @@ static long pt_event_snapshot_aux(struct perf_event 
*event,
         * Here, handle_nmi tells us if the tracing was on.
         * If the tracing was on, restart it.
         */
-       if (READ_ONCE(pt->handle_nmi))
+       if (READ_ONCE(pt->handle_nmi)) {
+               WRITE_ONCE(pt->resume_allowed, 1);
+               barrier();
                pt_config_start(event);
+               barrier();
+               WRITE_ONCE(pt->pause_allowed, 1);
+       }
 
        return ret;
 }
@@ -1923,7 +1984,9 @@ static __init int pt_init(void)
        if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
                pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG;
 
-       pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE;
+       pt_pmu.pmu.capabilities         |= PERF_PMU_CAP_EXCLUSIVE |
+                                          PERF_PMU_CAP_ITRACE |
+                                          PERF_PMU_CAP_AUX_PAUSE;
        pt_pmu.pmu.attr_groups           = pt_attr_groups;
        pt_pmu.pmu.task_ctx_nr           = perf_sw_context;
        pt_pmu.pmu.event_init            = pt_event_init;
diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h
index 0428019b92f4..480a5a311148 100644
--- a/arch/x86/events/intel/pt.h
+++ b/arch/x86/events/intel/pt.h
@@ -119,6 +119,8 @@ struct pt_filters {
  * @filters:           last configured filters
  * @handle_nmi:                do handle PT PMI on this cpu, there's an active 
event
  * @vmx_on:            1 if VMX is ON on this cpu
+ * @pause_allowed:     PERF_EF_PAUSE is allowed to stop tracing
+ * @resume_allowed:    PERF_EF_RESUME is allowed to start tracing
  * @output_base:       cached RTIT_OUTPUT_BASE MSR value
  * @output_mask:       cached RTIT_OUTPUT_MASK MSR value
  * @status:            cached RTIT_STATUS MSR value
@@ -132,6 +134,8 @@ struct pt {
        struct pt_filters       filters;
        int                     handle_nmi;
        int                     vmx_on;
+       int                     pause_allowed;
+       int                     resume_allowed;
        u64                     output_base;
        u64                     output_mask;
        u64                     status;
-- 
2.43.0


Reply via email to