[PATCH v2 1/7] arm64: dts: qcom: sc7280: Mark some nodes as 'reserved'

[Luca Weiss]

With the standard Qualcomm TrustZone setup, components such as lpasscc,
pdc_reset and watchdog shouldn't be touched by Linux. Mark them with
the status 'reserved' and reenable them in the chrome-common dtsi.

Signed-off-by: Luca Weiss <luca.we...@fairphone.com>
---
 arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 24 ++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sc7280.dtsi               |  8 +++++++-
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi 
b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
index 2e1cd219fc18..5d462ae14ba1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
@@ -46,6 +46,26 @@ wpss_mem: memory@9ae00000 {
        };
 };
 
+&lpass_aon {
+       status = "okay";
+};
+
+&lpass_core {
+       status = "okay";
+};
+
+&lpass_hm {
+       status = "okay";
+};
+
+&lpasscc {
+       status = "okay";
+};
+
+&pdc_reset {
+       status = "okay";
+};
+
 /* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
 &pmk8350_pon {
        status = "disabled";
@@ -84,6 +104,10 @@ &scm {
        dma-coherent;
 };
 
+&watchdog {
+       status = "okay";
+};
+
 &wifi {
        status = "okay";
 
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2af42d0ad99e..3f7f5c99eaf8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2316,6 +2316,7 @@ lpasscc: lpasscc@3000000 {
                        clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
                        clock-names = "iface";
                        #clock-cells = <1>;
+                       status = "reserved"; /* Owned by ADSP firmware */
                };
 
                lpass_rx_macro: codec@3200000 {
@@ -2467,6 +2468,7 @@ lpass_aon: clock-controller@3380000 {
                        clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
                        #clock-cells = <1>;
                        #power-domain-cells = <1>;
+                       status = "reserved"; /* Owned by ADSP firmware */
                };
 
                lpass_core: clock-controller@3900000 {
@@ -2477,6 +2479,7 @@ lpass_core: clock-controller@3900000 {
                        power-domains = <&lpass_hm 
LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
                        #clock-cells = <1>;
                        #power-domain-cells = <1>;
+                       status = "reserved"; /* Owned by ADSP firmware */
                };
 
                lpass_cpu: audio@3987000 {
@@ -2547,6 +2550,7 @@ lpass_hm: clock-controller@3c00000 {
                        clock-names = "bi_tcxo";
                        #clock-cells = <1>;
                        #power-domain-cells = <1>;
+                       status = "reserved"; /* Owned by ADSP firmware */
                };
 
                lpass_ag_noc: interconnect@3c40000 {
@@ -4243,6 +4247,7 @@ pdc_reset: reset-controller@b5e0000 {
                        compatible = "qcom,sc7280-pdc-global";
                        reg = <0 0x0b5e0000 0 0x20000>;
                        #reset-cells = <1>;
+                       status = "reserved"; /* Owned by firmware */
                };
 
                tsens0: thermal-sensor@c263000 {
@@ -5239,11 +5244,12 @@ msi-controller@17a40000 {
                        };
                };
 
-               watchdog@17c10000 {
+               watchdog: watchdog@17c10000 {
                        compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
                        reg = <0 0x17c10000 0 0x1000>;
                        clocks = <&sleep_clk>;
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "reserved"; /* Owned by Gunyah hyp */
                };
 
                timer@17c20000 {

-- 
2.42.0