On 4/20/21 1:11 AM, Nava kishore Manne wrote:
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index f532c59bb59b..877b43b3377d 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -445,6 +445,17 @@ config HISI_HIKEY_USB
> switching between the dual-role USB-C port and the USB-A host ports
> using only one USB controller.
>
> +config ZYNQ_AFI
> + tristate "Xilinx ZYNQ AFI support"
> + help
> + Zynq AFI driver support for writing to the AFI registers
> + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
> + the PS to the programmable logic (PL) through the AXI port.
> + This AXI port helps to establish the data path between the
> + PS and PL.In-order to establish the proper communication path
> + between PS and PL, the AXI port data path should be configured
> + with the proper Bus-width values
End that last sentence with a period ('.').
thanks.
--
~Randy
