On Tue, Apr 06, 2021 at 01:13:06PM +0300, Andy Shevchenko wrote:
> The PCI device IDs are defined with a prefix PCI_DEVICE_ID.
> There is no need to repeat the ID part at the end of each definition.
>
> Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Reviewed-by: Wong Vee Khee <vee.khee.w...@linux.intel.com>
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 60 +++++++++----------
> 1 file changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> index 3d9a57043af2..7f0ce373a63d 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> @@ -1053,41 +1053,41 @@ static int __maybe_unused intel_eth_pci_resume(struct
> device *dev)
> static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
> intel_eth_pci_resume);
>
> -#define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
> -#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30
> -#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31
> -#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32
> +#define PCI_DEVICE_ID_INTEL_QUARK 0x0937
> +#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30
> +#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31
> +#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
> /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
> * which are named PSE0 and PSE1
> */
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2
> -#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac
> -#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2
> -#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
> -#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID 0x7aac
> -#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID 0x7aad
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2
> +#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac
> +#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2
> +#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac
> +#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac
> +#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad
>
> static const struct pci_device_id intel_eth_pci_id_table[] = {
> - { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info)
> },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info)
> },
> - { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_phy0_info) },
> - { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_phy0_info) },
> - { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_phy1_info) },
> - { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, &adls_sgmii1g_phy0_info) },
> - { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, &adls_sgmii1g_phy1_info) },
> + { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
> + { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
> + { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
> + { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
> + { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
> {}
> };
> MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
> --
> 2.30.2
>
>
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