[PATCH V2 04/18] ARM: dts: imx7ulp: add the missing lpi2c nodes

[Clark Wang]

Add the missing lpi2c4/5 nodes for imx7ulp.

Signed-off-by: Clark Wang <xiaoning.w...@nxp.com>
---
V2 changes:
 - New patch added in V2
---
 arch/arm/boot/dts/imx7ulp.dtsi | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index eb0d4b8f624d..0c51fa79c0bc 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -22,8 +22,10 @@ aliases {
                gpio1 = &gpio_ptd;
                gpio2 = &gpio_pte;
                gpio3 = &gpio_ptf;
-               i2c0 = &lpi2c6;
-               i2c1 = &lpi2c7;
+               i2c0 = &lpi2c4;
+               i2c1 = &lpi2c5;
+               i2c2 = &lpi2c6;
+               i2c3 = &lpi2c7;
                mmc0 = &usdhc0;
                mmc1 = &usdhc1;
                serial0 = &lpuart4;
@@ -145,6 +147,31 @@ sec_jr1: jr@2000 {
                        };
                };
 
+               lpi2c4: lpi2c4@402b0000 {
+                       compatible = "fsl,imx7ulp-lpi2c";
+                       reg = <0x402b0000 0x10000>;
+                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pcc2 IMX7ULP_CLK_LPI2C4>,
+                                <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
+                       clock-names = "per", "ipg";
+                       assigned-clocks = <&pcc2 IMX7ULP_CLK_LPI2C4>;
+                       assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+                       assigned-clock-rates = <48000000>;
+                       status = "disabled";
+               };
+
+               lpi2c5: lpi2c5@402c0000 {
+                       compatible = "fsl,imx7ulp-lpi2c";
+                       reg = <0x402c0000 0x10000>;
+                       interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pcc2 IMX7ULP_CLK_LPI2C5>,
+                                <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
+                       clock-names = "per", "ipg";
+                       assigned-clocks = <&pcc2 IMX7ULP_CLK_LPI2C5>;
+                       assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+                       assigned-clock-rates = <48000000>;
+               };
+
                lpuart4: serial@402d0000 {
                        compatible = "fsl,imx7ulp-lpuart";
                        reg = <0x402d0000 0x1000>;
-- 
2.25.1