On Thu, Apr 01, 2021 at 01:10:48PM +0000, Liu, Yi L wrote: > > From: Jason Gunthorpe <j...@nvidia.com> > > Sent: Thursday, April 1, 2021 7:47 PM > [...] > > I'm worried Intel views the only use of PASID in a guest is with > > ENQCMD, but that is not consistent with the industry. We need to see > > normal nested PASID support with assigned PCI VFs. > > I'm not quire flow here. Intel also allows PASID usage in guest without > ENQCMD. e.g. Passthru a PF to guest, and use PASID on it without ENQCMD.
Then you need all the parts, the hypervisor calls from the vIOMMU, and you can't really use a vPASID. I'm not sure how Intel intends to resolve all of this. > > > - this per-ioasid SVA operations is not aligned with the native SVA usage > > > model. Native SVA bind is per-device. > > > > Seems like that is an error in native SVA. > > > > SVA is a particular mode of the PASID's memory mapping table, it has > > nothing to do with a device. > > I think it still has relationship with device. This is determined by the > DMA remapping hierarchy in hardware. e.g. Intel VT-d, the DMA isolation is > enforced first in device granularity and then PASID granularity. SVA makes > usage of both PASID and device granularity isolation. When the device driver authorizes a PASID the VT-d stuff should setup the isolation parameters for the give pci_device and PASID. Do not leak implementation details like this as uAPI. Authorization and memory map are distinct ideas with distinct interfaces. Do not mix them. Jason
