Hi Brad, On 28/03/21 06:59PM, Brad Larson wrote: > Add new vendor Pensando Systems Elba SoC compatible > string and convert to json-schema. > > Signed-off-by: Brad Larson <[email protected]> > --- > .../bindings/spi/cadence-quadspi.txt | 68 -------- > .../bindings/spi/cadence-quadspi.yaml | 153 ++++++++++++++++++ > 2 files changed, 153 insertions(+), 68 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt > create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml > > diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt > b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt > deleted file mode 100644 > index 8ace832a2d80..000000000000 > --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt > +++ /dev/null > @@ -1,68 +0,0 @@ > -* Cadence Quad SPI controller > - > -Required properties: > -- compatible : should be one of the following: > - Generic default - "cdns,qspi-nor". > - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". > - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". > - For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". > -- reg : Contains two entries, each of which is a tuple consisting of a > - physical address and length. The first entry is the address and > - length of the controller register set. The second entry is the > - address and length of the QSPI Controller data area. > -- interrupts : Unit interrupt specifier for the controller interrupt. > -- clocks : phandle to the Quad SPI clock. > -- cdns,fifo-depth : Size of the data FIFO in words. > -- cdns,fifo-width : Bus width of the data FIFO in bytes. > -- cdns,trigger-address : 32-bit indirect AHB trigger address. > - > -Optional properties: > -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. > -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch > - the read data rather than the QSPI clock. Make sure that QSPI return > - clock is populated on the board before using this property. > - > -Optional subnodes: > -Subnodes of the Cadence Quad SPI controller are spi slave nodes with > additional > -custom properties: > -- cdns,read-delay : Delay for read capture logic, in clock cycles > -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master > - mode chip select outputs are de-asserted between > - transactions. > -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being > - de-activated and the activation of another. > -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current > - transaction and deasserting the device chip select > - (qspi_n_ss_out). > -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low > - and first bit transfer. > -- resets : Must contain an entry for each entry in reset-names. > - See ../reset/reset.txt for details. > -- reset-names : Must include either "qspi" and/or "qspi-ocp". > - > -Example: > - > - qspi: spi@ff705000 { > - compatible = "cdns,qspi-nor"; > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <0xff705000 0x1000>, > - <0xffa00000 0x1000>; > - interrupts = <0 151 4>; > - clocks = <&qspi_clk>; > - cdns,is-decoded-cs; > - cdns,fifo-depth = <128>; > - cdns,fifo-width = <4>; > - cdns,trigger-address = <0x00000000>; > - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; > - reset-names = "qspi", "qspi-ocp"; > - > - flash0: n25q00@0 { > - ... > - cdns,read-delay = <4>; > - cdns,tshsl-ns = <50>; > - cdns,tsd2d-ns = <50>; > - cdns,tchsh-ns = <4>; > - cdns,tslch-ns = <4>; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml > b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml > new file mode 100644 > index 000000000000..94d631045153 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml > @@ -0,0 +1,153 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cadence Quad SPI controller > + > +maintainers: > + - Ramuthevar Vadivel Murugan <[email protected]> > + - Brad Larson <[email protected]> > + > +properties: > + compatible: > + contains: > + enum: > + - cdns,qspi-nor # Generic default > + - ti,k2g-qspi # TI 66AK2G SoC > + - ti,am654-ospi # TI AM654 SoC > + - intel,lgm-qspi # Intel LGM SoC > + - pensando,cdns-qspi # Pensando Elba SoC
Wouldn't this allow any combination of all 5 strings? So for example this would allow "ti,am654-ospi", "pensando,cdns-qspi" which is obviously not correct. I sent a patch recently [0] that does this correctly and it has gotten Rob's blessing. So I suggest you build your patch on top of that. [...] [0] https://patchwork.kernel.org/project/spi-devel-general/patch/[email protected]/ -- Regards, Pratyush Yadav Texas Instruments Inc.
