s/untile/until/
s/souce/source/
s/divier/divider/
Signed-off-by: Bhaskar Chowdhury <unixbhas...@gmail.com>
---
Changes from V1:
Krzysztof spotted a grammatical flaw left over ...so corrected..
drivers/cpufreq/s5pv210-cpufreq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/cpufreq/s5pv210-cpufreq.c
b/drivers/cpufreq/s5pv210-cpufreq.c
index 69786e5bbf05..af1ac3f6e4b8 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -378,7 +378,7 @@ static int s5pv210_target(struct cpufreq_policy *policy,
unsigned int index)
/*
* 6. Turn on APLL
* 6-1. Set PMS values
- * 6-2. Wait untile the PLL is locked
+ * 6-2. Wait until the PLL is locked
*/
if (index == L0)
writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);
@@ -390,7 +390,7 @@ static int s5pv210_target(struct cpufreq_policy *policy,
unsigned int index)
} while (!(reg & (0x1 << 29)));
/*
- * 7. Change souce clock from SCLKMPLL(667Mhz)
+ * 7. Change source clock from SCLKMPLL(667Mhz)
* to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
* (667/4=166)->(200/4=50)Mhz
*/
@@ -439,7 +439,7 @@ static int s5pv210_target(struct cpufreq_policy *policy,
unsigned int index)
}
/*
- * L4 level need to change memory bus speed, hence onedram clock divier
+ * L4 level needs to change memory bus speed, hence onedram clock
divider
* and memory refresh parameter should be changed
*/
if (bus_speed_changing) {
--
2.26.2
