On Tue, Feb 16, 2021 at 12:19:39AM +0100, Adrien Grassein wrote:
> Add description and pinmuxing for uarts.
>
> Signed-off-by: Adrien Grassein <adrien.grass...@gmail.com>
> ---
> .../boot/dts/freescale/imx8mm-nitrogen-r2.dts | 53 ++++++++++++++++++-
> 1 file changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
> index 22acde0f3ba8..3c5b692f6ad1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
> @@ -206,6 +206,15 @@ rtc@68 {
> };
> };
>
> +/* BT */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + assigned-clocks = <&clk IMX8MM_CLK_UART1>;
I see you have it also for uart2 - what is the purpose of it? What does
the "assigned-clocks" property alone do?
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> /* console */
> &uart2 {
> pinctrl-names = "default";
> @@ -215,6 +224,23 @@ &uart2 {
> status = "okay";
> };
>
> +/* J15 */
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + assigned-clocks = <&clk IMX8MM_CLK_UART3>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +/* J9 */
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + assigned-clocks = <&clk IMX8MM_CLK_UART4>;
> + status = "okay";
> +};
> +
> /* eMMC */
> &usdhc1 {
> bus-width = <8>;
> @@ -353,6 +379,15 @@ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
> >;
> };
>
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
> + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
> + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
> + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
> + >;
> + };
> +
> pinctrl_uart2: uart2grp {
> fsl,pins = <
> MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> @@ -360,6 +395,22 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> >;
> };
>
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
> + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
> + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
> + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
> + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
> + >;
> + };
> +
> pinctrl_usbotg1: usbotg1grp {
> fsl,pins = <
> MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x16
> @@ -370,7 +421,7 @@ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x156
> pinctrl_usbotg2: usbotg2grp {
> fsl,pins = <
> MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x16
> - MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x156
> + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x15
This is not relevant to the topic.
Best regards,
Krzysztof
