On 01-01-08 22:44, H. Peter Anvin wrote:
Rene Herman wrote:
On 01-01-08 22:15, H. Peter Anvin wrote:
I have mentioned this before... I think writing zero to port 0xf0
would be an acceptable pause interface (to the extent where we need
an I/O port) except on 386 with 387 present; on those systems we can
fall back to 0x80.
PII 400 / Intel 440 BX (PIIX4):
[EMAIL PROTECTED]:~/port80$ su -c ./portime
out 0x80: 544 cycles
in 0x80: 254 cycles
in 0x61: 254 cycles
out 0xf0: 544 cycles
The Intel PIIX/PIIX3 datasheet specifically mentions that both reads
and writes at 0xf0 "flow through to the ISA bus".
However, more complete, it says:
"Writing to this register causes the PIIX/PIIX3 to assert IGNNE#. The
PIIX/PIIX3 also negates IRQ13 (internal to the PIIX). Note that IGNNE#
is not asserted unless FERR# is active. Reads/writes flow through to
the ISA bus".
We don't want the side-effects, do we?
Yes, we do. It's exactly this side effect which makes this safer than
either 0x80 or 0xED -- it's a port that *guaranteed* can't be reclaimed
for other purposes without breaking MS-DOS compatibility.
I see that with CR0.NE set (*) we indeed don't care about IGNNE#...
However, I'm worried about this comment in arch/x86/kernel/i8259_32.c
===
/*
* New motherboards sometimes make IRQ 13 be a PCI interrupt,
* so allow interrupt sharing.
*/
===
Is it really safe to just blindly negate IRQ13 on everything out there, from
regular PC through funky embedded thingies?
(*) bit 5:
[EMAIL PROTECTED]:~/src/local$ ./smsw
msw: 0x3b
Rene.
/* gcc -W -Wall -o smsw smsw.c */
#include <stdio.h>
#include <stdint.h>
int main(void)
{
uint16_t msw;
asm ("smsw %0": "=r" (msw));
printf("msw: %#hx\n", msw);
return 0;
}
