> -----Original Message-----
> From: Moritz Fischer <m...@kernel.org>
> Sent: Wednesday, January 27, 2021 4:39 AM
> To: Ardelean, Alexandru <alexandru.ardel...@analog.com>
> Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; mturque...@baylibre.com; sb...@kernel.org;
> robh...@kernel.org; l...@metafoo.de; linux-f...@vger.kernel.org;
> m...@kernel.org; Bogdan, Dragos <dragos.bog...@analog.com>
> Subject: Re: [PATCH v2 1/3] clk: axi-clkgen: remove ARCH dependency in Kconfig
> 
> Alexandru,
> 
> On Tue, Jan 26, 2021 at 01:08:24PM +0200, Alexandru Ardelean wrote:
> > The intent is to be able to run this driver to access the IP core in
> > setups where FPGA board is also connected via a PCIe bus. In such
> > cases the number of combinations explodes, where the host system can
> > be an x86 with Xilinx Zynq/ZynqMP/Microblaze board connected via PCIe.
> > Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
> >
> > To accommodate for these cases, this change removes the limitation for
> > this driver to be compilable only on Zynq/Microblaze architectures.
> >
> > Signed-off-by: Dragos Bogdan <dragos.bog...@analog.com>
> > Signed-off-by: Alexandru Ardelean <alexandru.ardel...@analog.com>
> > ---
> >  drivers/clk/Kconfig | 1 -
> >  1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
> > 85856cff506c..d8c2d4593926 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -247,7 +247,6 @@ config CLK_TWL6040
> >
> >  config COMMON_CLK_AXI_CLKGEN
> >     tristate "AXI clkgen driver"
> > -   depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
> Umhhh ... no dependencies? How are you accessing your registers? You seem to
> be using device tree, probably:
> 
>       depends on HAS_IOMEM || COMPILE_TEST
>       depends on OF
> 
> at least? Please double check your dependencies.

Agreed.
Will re-spin.
This is a n00b mistake on my part

Thanks

> >     help
> >       Support for the Analog Devices axi-clkgen pcore clock generator for
> Xilinx
> >       FPGAs. It is commonly used in Analog Devices' reference designs.
> > --
> > 2.17.1
> >
> 
> - Moritz

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