Hi, Dear X86 Maintainers, >On Mon, Jan 04, 2021 at 07:42:28PM +0000, Fenghua Yu wrote: > > On Tue, Nov 24, 2020 at 08:52:41PM +0000, Fenghua Yu wrote: > > A bus lock [1] is acquired through either split locked access to > > writeback (WB) memory or any locked access to non-WB memory. This is > > typically >1000 cycles slower than an atomic operation within > > a cache line. It also disrupts performance on other cores. Just a friendly reminder. Any comment on this series? There hasn't been any comment since it was posted.
This series can be applied cleanly to v5.11-rc5 and pass all of our tests. If you want me to repost this series, I can do that too. Thanks! -Fenghua
