On Wed, Jan 06, 2021 at 04:42:59PM +0900, Namhyung Kim wrote:
> On Sun, Dec 13, 2020 at 10:39 PM Leo Yan <leo....@linaro.org> wrote:
> >
> > Add dimensions for load miss and its percentage calculation, which is to
> > be displayed in the single cache line output.
> >
> > Signed-off-by: Leo Yan <leo....@linaro.org>
> > ---
> > tools/perf/builtin-c2c.c | 107 +++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 107 insertions(+)
> >
> > diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
> > index 00014e3d81fa..27745340c14a 100644
> > --- a/tools/perf/builtin-c2c.c
> > +++ b/tools/perf/builtin-c2c.c
> > @@ -624,6 +624,10 @@ tot_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
> > (stats)->rmt_hitm + \
> > (stats)->rmt_hit)
> >
> > +#define TOT_LD_MISS(stats) \
> > + ((stats)->lcl_dram + \
> > + (stats)->rmt_dram)
> > +
>
> Is this true always? I'm not sure if there's a case where stores can go to
> DRAM
> directly.. maybe like a kind of uncached accesses.
Firstly, from my understanding, the uncached accesses are not accounted
in the "load miss" metrics. You could see there have other two metrics
"stats->st_uncache" and "stats->ld_uncache" which present the store
uncached and load uncached respectively.
Furthermore, based on the function total_records(), it uses below
formula to account the total load accesses:
lclmiss = stats->lcl_dram +
stats->rmt_dram +
stats->rmt_hitm +
stats->rmt_hit;
ldcnt = lclmiss +
stats->ld_fbhit +
stats->ld_l1hit +
stats->ld_l2hit +
stats->ld_llchit +
stats->lcl_hitm;
So this patch series classifies these metrics into two numbers: load hit
and load miss; load hit is considered as hit at any cache levels
(L1, L2, LLC and even remote cache), the load miss is accounted with the
rest metrics (lcl_dram + rmt_dram).
> Also it can be a static function..
Yeah, will fix.
Thanks,
Leo
